{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T04:23:22Z","timestamp":1729657402135,"version":"3.28.0"},"reference-count":23,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,11]]},"DOI":"10.1109\/isda.2010.5687196","type":"proceedings-article","created":{"date-parts":[[2011,1,13]],"date-time":"2011-01-13T16:33:25Z","timestamp":1294936405000},"page":"610-614","source":"Crossref","is-referenced-by-count":5,"title":["Multi-width fixed-point coding based on reprogrammable hardware implementation of a multi-layer perceptron neural network for alertness classification"],"prefix":"10.1109","author":[{"given":"Ahmed Ghazi","family":"Bla","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Khaled","family":"Ben Khalifa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mohamed","family":"Boubaker","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mohamed Hedi","family":"Bedoui","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/TCSI.2009.2025803"},{"key":"ref11","article-title":"Fixed-Point Optimization Utility for C and C++ Based Digital Signal Processing Programs","volume":"45","author":"kum","year":"1998","journal-title":"IEEE Transactions on Circuits and Systems II"},{"key":"ref12","first-page":"271","article-title":"A Methodology and Design Environment for DSP ASIC Fixed Point Refinement","author":"kim","year":"1999","journal-title":"Dans Proceedings of the Design Automation and Test in Europe Conference (DATE 99)"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"840","DOI":"10.1109\/82.868453","article-title":"AUTOSCALER for C: An optimizing floating-point to integer C program converter for fixed-point digital signal processors","volume":"47","author":"kum","year":"2000","journal-title":"IEEE Transactions on Circuits and Systems II - Analog and Digital Signal Processing"},{"key":"ref14","first-page":"355","article-title":"Bit-width optimization for configurable dsp's by multi-intervalanalysis","volume":"1","author":"benedetti","year":"2000","journal-title":"Dans Signals Systems and Computers 2000 Conference Record of the Thirty-Fourth Asilomar Conference on"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1145\/349299.349317"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1023\/B:NUMA.0000049462.70970.b6"},{"key":"ref17","first-page":"95","article-title":"Interval Computations: Introduction, Uses, and Resources","volume":"2","author":"kearfott","year":"1996","journal-title":"Euromath Bulletin"},{"key":"ref18","article-title":"&#x00AB;Fixed-Point Optimization Utility for C and C++ Based Digital Signal Processing Programs","author":"kim","year":"1995","journal-title":"Dans Workshop on VLSI and Signal Processing '95"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1109\/ICASSP.2001.941121"},{"key":"ref4","first-page":"103","article-title":"FPGA Implementation of High Precision Feedforward Networks","author":"anguita","year":"2006"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/EMS.2009.13"},{"key":"ref6","article-title":"I.CA.R. Efficient MLP Digital Implementation on FPGA. Italien National Research Concil viale dele Scienze, 90128 Palermo","author":"vitabile","year":"2005","journal-title":"Italy and Dipartimento Ingegneria Informatica-University of Palermo"},{"key":"ref5","first-page":"167","article-title":"Hardware codesign for embedded implementation of Neural Networks","volume":"4419","author":"torres","year":"2007","journal-title":"Springerlink"},{"key":"ref8","first-page":"283","article-title":"Implementation of an LVQ neural network with a variable size:algorithmic specification, architectural exploration and optimized implementation on FPGA devices","author":"boubaker","year":"2009"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/TNN.2006.883002"},{"key":"ref2","article-title":"Artificial neural networks to extract knowledge from eeg","author":"ben","year":"2005","journal-title":"The Fifth IASTED International Conference in Biomedical Engineering BioMED"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1016\/S1350-4533(02)00030-9"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/12.57043"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1109\/ISSS.1998.730590"},{"doi-asserted-by":"publisher","key":"ref22","DOI":"10.1109\/DATE.2002.998351"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.1109\/ICCD.1998.727023"},{"year":"2004","author":"constantinides","article-title":"Synthesis and Optimization of DSP Algorithms","key":"ref23"}],"event":{"name":"2010 10th International Conference on Intelligent Systems Design and Applications (ISDA)","start":{"date-parts":[[2010,11,29]]},"location":"Cairo, Egypt","end":{"date-parts":[[2010,12,1]]}},"container-title":["2010 10th International Conference on Intelligent Systems Design and Applications"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5681599\/5687016\/05687196.pdf?arnumber=5687196","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,7]],"date-time":"2019-06-07T16:47:12Z","timestamp":1559926032000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5687196\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,11]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/isda.2010.5687196","relation":{},"subject":[],"published":{"date-parts":[[2010,11]]}}}