{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,22]],"date-time":"2025-10-22T05:19:41Z","timestamp":1761110381439,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,12]]},"DOI":"10.1109\/ised.2017.8303922","type":"proceedings-article","created":{"date-parts":[[2018,3,1]],"date-time":"2018-03-01T16:58:31Z","timestamp":1519923511000},"page":"1-5","source":"Crossref","is-referenced-by-count":4,"title":["CIFR: A complete in-place fault remapping strategy for CMP cache using dynamic reuse distance"],"prefix":"10.1109","author":[{"given":"Avishek","family":"Choudhury","sequence":"first","affiliation":[]},{"given":"Biplab K","family":"Sikdar","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IPDS.1995.395819"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2010.5452017"},{"key":"ref12","article-title":"REMEDIATE: a scalable fault-tolerant architecture for low-power NUCA cache in tiled CMPs","author":"banaiyan mofrad","year":"2013","journal-title":"Proc IGCC"},{"key":"ref13","doi-asserted-by":"crossref","DOI":"10.7873\/DATE2014.073","article-title":"Spatial pattern prediction based management of faulty data caches","author":"keramidas","year":"2014","journal-title":"Proceedings of the Design Automation & Test in Europe Conference"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.43"},{"key":"ref4","first-page":"113118","article-title":"65nmsub-threshold 11t-sram for ultra low voltage applications","author":"moradi","year":"2008","journal-title":"International Symposium on System-on-Chip"},{"key":"ref3","first-page":"3849","article-title":"Low-voltage on-chip cache architecture using heterogeneous cell sizes for multi-core processors","author":"ghasemi","year":"2011","journal-title":"IEEE International Symposium on High-Performance Computer Architecture"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.52"},{"journal-title":"Error Control Coding","year":"2004","author":"lin","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/12.21141"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/12.210168"},{"key":"ref2","article-title":"Using a Flexible Fault-Tolerant Cache to Improve Reliability for Ultra Low","volume":"14","author":"banaiyanmofrad","year":"2015","journal-title":"Voltage Operation ACM Transactions on Embedded Computing Systems"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MCD.2005.1388765"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1594233.1594309"}],"event":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","start":{"date-parts":[[2017,12,18]]},"location":"Durgapur","end":{"date-parts":[[2017,12,20]]}},"container-title":["2017 7th International Symposium on Embedded Computing and System Design (ISED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8296056\/8303903\/08303922.pdf?arnumber=8303922","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,11]],"date-time":"2019-10-11T23:46:48Z","timestamp":1570837608000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8303922\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,12]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/ised.2017.8303922","relation":{},"subject":[],"published":{"date-parts":[[2017,12]]}}}