{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T06:46:01Z","timestamp":1725432361120},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,12]]},"DOI":"10.1109\/ised.2017.8303940","type":"proceedings-article","created":{"date-parts":[[2018,3,1]],"date-time":"2018-03-01T21:58:31Z","timestamp":1519941511000},"page":"1-5","source":"Crossref","is-referenced-by-count":0,"title":["OTORNoC: Optical tree of rings network on chip for 1000 core systems"],"prefix":"10.1109","author":[{"given":"Soumyajit","family":"Poddar","sequence":"first","affiliation":[]},{"family":"Suraj","sequence":"additional","affiliation":[]},{"given":"Amit Kumar","family":"Yadav","sequence":"additional","affiliation":[]},{"given":"Hafizur","family":"Rahaman","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"crossref","first-page":"477","DOI":"10.1145\/1854273.1854332","article-title":"ATAC: A 1000-core cache-coherent processor with on-chip optical network","author":"kurian","year":"2010","journal-title":"Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques (PACT)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457114"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.4108\/ICST.SIMUTOOLS2008.3027"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2839301"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2567930"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2009.5071460"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2012.6187477"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.78"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2600072"},{"key":"ref1","first-page":"105","article-title":"A network on chip architecture and design methodology","author":"kumar","year":"2002","journal-title":"Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2002"}],"event":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","start":{"date-parts":[[2017,12,18]]},"location":"Durgapur","end":{"date-parts":[[2017,12,20]]}},"container-title":["2017 7th International Symposium on Embedded Computing and System Design (ISED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8296056\/8303903\/08303940.pdf?arnumber=8303940","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,12]],"date-time":"2019-10-12T03:46:48Z","timestamp":1570852008000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8303940\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,12]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/ised.2017.8303940","relation":{},"subject":[],"published":{"date-parts":[[2017,12]]}}}