{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T03:04:25Z","timestamp":1725419065318},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,12]]},"DOI":"10.1109\/ised.2017.8303948","type":"proceedings-article","created":{"date-parts":[[2018,3,1]],"date-time":"2018-03-01T16:58:31Z","timestamp":1519923511000},"page":"1-4","source":"Crossref","is-referenced-by-count":0,"title":["A CAD approach for on-chip PDN with power and supply noise reduction for multi-voltage SOCS in pre-layout stage"],"prefix":"10.1109","author":[{"given":"Moumita","family":"Chakraborty","sequence":"first","affiliation":[]},{"given":"Debasri","family":"Saha","sequence":"additional","affiliation":[]},{"given":"Amlan","family":"Chakrabarti","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/101.666591"},{"key":"ref11","first-page":"309","article-title":"Post-Placement Voltage Island Generation under Performance Requirement","author":"wu","year":"2005","journal-title":"ICCAD"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147023"},{"key":"ref13","first-page":"641","article-title":"Post-Placement Voltage Island Generation","author":"ching","year":"2006","journal-title":"ICCAD"},{"journal-title":"Cadence","article-title":"Architecting, Designing, Implementing, and Verifying Low-Power Digital Integrated Circuits","year":"2007","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364663"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9781139166980"},{"journal-title":"Methodologies for Modeling Simultaneous Switching Noise in Multi-Layered Packages and Boards","year":"2002","author":"chun","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/505388.505405"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/369691.369737"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-005-6761-x"},{"key":"ref7","first-page":"217","article-title":"A fast onchip decoupling capacitance budgeting algorithm using macromodeling and linear programming","author":"zhao","year":"2006","journal-title":"Proc Des Autom Conf"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/224081.224083"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2017437"},{"key":"ref9","article-title":"A mimimum Decap allocation technique based on simultaneous switching for nanoscale SoC","author":"shimazaki","year":"2009","journal-title":"Proc IEEE Custom Integrated Circuits Conference"}],"event":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","start":{"date-parts":[[2017,12,18]]},"location":"Durgapur","end":{"date-parts":[[2017,12,20]]}},"container-title":["2017 7th International Symposium on Embedded Computing and System Design (ISED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8296056\/8303903\/08303948.pdf?arnumber=8303948","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,4,2]],"date-time":"2018-04-02T16:44:29Z","timestamp":1522687469000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8303948\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,12]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/ised.2017.8303948","relation":{},"subject":[],"published":{"date-parts":[[2017,12]]}}}