{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,22]],"date-time":"2025-10-22T05:20:37Z","timestamp":1761110437477},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,12]]},"DOI":"10.1109\/ised.2018.8704108","type":"proceedings-article","created":{"date-parts":[[2019,5,2]],"date-time":"2019-05-02T18:53:59Z","timestamp":1556823239000},"page":"80-84","source":"Crossref","is-referenced-by-count":4,"title":["ReMiT: Redundancy Migration for Latency Aware Fault Tolerant Cache Design in Multicore"],"prefix":"10.1109","author":[{"given":"Avishek","family":"Choudhury","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Brototi","family":"Mondal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Biplab K","family":"Sikdar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IPDS.1995.395819"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2010.5452017"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IGCC.2013.6604500"},{"key":"ref13","doi-asserted-by":"crossref","DOI":"10.7873\/DATE2014.073","article-title":"Spatial pattern prediction based management of faulty data caches","author":"keramidas","year":"2014","journal-title":"Proceedings of the Design Automation &amp; Test in Europe Conference"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.43"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2007.4601909"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISED.2017.8303922"},{"key":"ref4","first-page":"113","article-title":"65nm-subthreshold 11t-sram for ultra low voltage applications","author":"moradi","year":"2008","journal-title":"International Symposium on System-on-Chip"},{"key":"ref3","first-page":"38","article-title":"Low-voltage on-chip cache architecture using heterogeneous cell sizes for multi-core processors","author":"ghasemi","year":"2011","journal-title":"IEEE International Symposium on High-Performance Computer Architecture"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.52"},{"journal-title":"Error Control Coding (2nd Edition)","year":"2004","author":"lin","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/12.21141"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/12.210168"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2629566"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MCD.2005.1388765"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1594233.1594309"}],"event":{"name":"2018 8th International Symposium on Embedded Computing and System Design (ISED)","start":{"date-parts":[[2018,12,13]]},"location":"Cochin, India","end":{"date-parts":[[2018,12,15]]}},"container-title":["2018 8th International Symposium on Embedded Computing and System Design (ISED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8698774\/8703880\/08704108.pdf?arnumber=8704108","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,20]],"date-time":"2019-05-20T18:59:30Z","timestamp":1558378770000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8704108\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,12]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/ised.2018.8704108","relation":{},"subject":[],"published":{"date-parts":[[2018,12]]}}}