{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T12:19:05Z","timestamp":1725452345955},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,12]]},"DOI":"10.1109\/isicir.2014.7029573","type":"proceedings-article","created":{"date-parts":[[2015,2,10]],"date-time":"2015-02-10T09:52:27Z","timestamp":1423561947000},"page":"103-106","source":"Crossref","is-referenced-by-count":4,"title":["An improved scan cell ordering method using the scan cells with complementary outputs"],"prefix":"10.1109","author":[{"given":"Mengyang","family":"Li","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Aijiao","family":"Cui","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tingting","family":"Yu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805616"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2002.808429"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2005.62"},{"key":"1","doi-asserted-by":"crossref","DOI":"10.1007\/b117406","author":"bushnell","year":"2002","journal-title":"Essentials of Electronic Testing for Digital Memory and Mixed-Signal VLSI Circuits"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041833"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391680"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894297"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-0928-2"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2002.1011129"},{"key":"8","first-page":"488","article-title":"Efficient scan chain design for power minimization during scan testing under routing constraint","author":"bonhmme","year":"2003","journal-title":"IEEE Int Test Conf"},{"key":"11","first-page":"1018","article-title":"A power-efficient scan tree design by exploring the Q'-D connection","author":"chen","year":"2013","journal-title":"IEEE Int Symp on Circuits and Systems"}],"event":{"name":"2014 International Symposium on Integrated Circuits (ISIC)","start":{"date-parts":[[2014,12,10]]},"location":"Singapore","end":{"date-parts":[[2014,12,12]]}},"container-title":["2014 International Symposium on Integrated Circuits (ISIC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7005969\/7029433\/07029573.pdf?arnumber=7029573","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,20]],"date-time":"2019-08-20T16:35:45Z","timestamp":1566318945000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7029573\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,12]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/isicir.2014.7029573","relation":{},"subject":[],"published":{"date-parts":[[2014,12]]}}}