{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T08:55:24Z","timestamp":1725440124894},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,12]]},"DOI":"10.1109\/isicir.2016.7829675","type":"proceedings-article","created":{"date-parts":[[2017,1,26]],"date-time":"2017-01-26T18:10:09Z","timestamp":1485454209000},"page":"1-5","source":"Crossref","is-referenced-by-count":0,"title":["Co-mitigating circuit PBTI and HCI aging considering NMOS transistor stacking effect"],"prefix":"10.1109","author":[{"family":"Maoxiang Yi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Yingxian Gan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Zhengfeng Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Huaguo Liang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"4002","article-title":"Channel Hot Carrier Degradation Mechanism in Long\/Short Channel n-FinFETs","author":"moonju","year":"2013","journal-title":"IEEE Transactions on Electron Devices"},{"key":"ref11","first-page":"1","article-title":"Experimental Study on Positive Bias Temperature Instability of SOI nMOSFETs with High-k Gate Dielectrics","author":"li","year":"2014","journal-title":"Acta Scientiarum Naturalium Universitatis Pekinensis"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/224818.224825"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364650"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2012.6263957"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.48"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2037637"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2214478"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090649"},{"key":"ref8","first-page":"75","article-title":"Joint Logic Restructuring and Pin Reordering against NBTI-Induced Performance Degradation","author":"wu","year":"2009","journal-title":"Design Automation Test in Europe Conf Exhibition"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2009.4810264"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2008.919322"},{"key":"ref1","first-page":"1044","article-title":"PBTI response to interfacial layer thickness variation in Hf-based HKMG nFETs","author":"loannou","year":"2010","journal-title":"International Reliability Physics Symposium"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2013.6523590"}],"event":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","start":{"date-parts":[[2016,12,12]]},"location":"Singapore","end":{"date-parts":[[2016,12,14]]}},"container-title":["2016 International Symposium on Integrated Circuits (ISIC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7822827\/7829673\/07829675.pdf?arnumber=7829675","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,4,6]],"date-time":"2018-04-06T00:51:08Z","timestamp":1522975868000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7829675\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,12]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/isicir.2016.7829675","relation":{},"subject":[],"published":{"date-parts":[[2016,12]]}}}