{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,21]],"date-time":"2025-11-21T11:25:35Z","timestamp":1763724335457,"version":"3.28.0"},"reference-count":7,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,12]]},"DOI":"10.1109\/isicir.2016.7829683","type":"proceedings-article","created":{"date-parts":[[2017,1,26]],"date-time":"2017-01-26T23:10:09Z","timestamp":1485472209000},"page":"1-4","source":"Crossref","is-referenced-by-count":6,"title":["A hardware framework for on-chip FPGA acceleration"],"prefix":"10.1109","author":[{"given":"Andrea","family":"Lomuscio","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gian Carlo","family":"Cardarilli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alberto","family":"Nannarelli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marco","family":"Re","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","article-title":"Intel Begins Shipping Xeon Chips With FPGA Accelerators","author":"burt","year":"2016","journal-title":"eWeek"},{"year":"2014","author":"crockett","journal-title":"The Zynq Book Embedded Processing with the Arm Cortex-A9 on the Xilinx Zynq-7000 All Programmable Soc","key":"ref3"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/ISSPIT.2015.7394346"},{"key":"ref5","article-title":"FPGA Acceleration by Dynamically-Loaded Hardware Libraries","author":"lomuscio","year":"2016","journal-title":"DTU Compute Technical Report-2016&#x2013;03"},{"year":"0","author":"cowlishaw","article-title":"General Decimal Arithmetic","key":"ref7"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/MM.2012.20"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"4","DOI":"10.1109\/MM.2008.50","article-title":"Accelerator Architectures","volume":"28","author":"patel","year":"2008","journal-title":"IEEE Micro Magazine"}],"event":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","start":{"date-parts":[[2016,12,12]]},"location":"Singapore","end":{"date-parts":[[2016,12,14]]}},"container-title":["2016 International Symposium on Integrated Circuits (ISIC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7822827\/7829673\/07829683.pdf?arnumber=7829683","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,4,6]],"date-time":"2018-04-06T04:50:47Z","timestamp":1522990247000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7829683\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,12]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/isicir.2016.7829683","relation":{},"subject":[],"published":{"date-parts":[[2016,12]]}}}