{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,9]],"date-time":"2025-04-09T06:07:53Z","timestamp":1744178873366},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,9]]},"DOI":"10.1109\/islped.2013.6629258","type":"proceedings-article","created":{"date-parts":[[2013,12,17]],"date-time":"2013-12-17T20:47:27Z","timestamp":1387313247000},"page":"3-8","source":"Crossref","is-referenced-by-count":19,"title":["Compiler assisted dynamic register file in GPGPU"],"prefix":"10.1109","author":[{"given":"Naifeng","family":"Jing","sequence":"first","affiliation":[]},{"given":"Haopeng","family":"Liu","sequence":"additional","affiliation":[]},{"given":"Yao","family":"Lu","sequence":"additional","affiliation":[]},{"given":"Xiaoyao","family":"Liang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919648"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522331"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485952"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1145\/2254756.2254787"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000094"},{"key":"3","doi-asserted-by":"crossref","DOI":"10.1109\/HPCA.2013.6522314","article-title":"Technology comparison for large last-level caches (l3cs): Low-leakage sram, low write-energy stt-ram, and refresh-optimized edram","author":"chang","year":"2013","journal-title":"Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture (HPCA)"},{"journal-title":"Nvidia's Next Generation CUDA Compute Architecture Fermi","year":"0","key":"2"},{"year":"0","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.22"},{"key":"7","article-title":"Process variation tolerant register files based on dynamic memories","author":"liang","year":"2007","journal-title":"Workshop on Architectural Support for Gigascale Integration (ASGI-07) in Conjunction with ISCA"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.40"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2006.1705371"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669140"},{"key":"9","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2366231.2337161","article-title":"RAIDR: Retention-aware intelligent DRAM refresh","author":"liu","year":"2012","journal-title":"Proceedings of the 21st International Symposium on Computer Architecture"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.13"}],"event":{"name":"2013 IEEE International Symposium on Low Power Electronics and Design (ISLPED)","start":{"date-parts":[[2013,9,4]]},"location":"Beijing, China","end":{"date-parts":[[2013,9,6]]}},"container-title":["International Symposium on Low Power Electronics and Design (ISLPED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6613639\/6629247\/06629258.pdf?arnumber=6629258","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,3,20]],"date-time":"2022-03-20T00:08:58Z","timestamp":1647734938000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6629258\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,9]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/islped.2013.6629258","relation":{},"subject":[],"published":{"date-parts":[[2013,9]]}}}