{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,4]],"date-time":"2025-04-04T19:44:02Z","timestamp":1743795842074},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,9]]},"DOI":"10.1109\/islped.2013.6629291","type":"proceedings-article","created":{"date-parts":[[2013,12,17]],"date-time":"2013-12-17T20:47:27Z","timestamp":1387313247000},"page":"181-186","source":"Crossref","is-referenced-by-count":6,"title":["Minimum supply voltage for sequential logic circuits in a 22nm technology"],"prefix":"10.1109","author":[{"given":"Chia-Hsiang","family":"Chen","sequence":"first","affiliation":[]},{"given":"Keith","family":"Bowman","sequence":"additional","affiliation":[]},{"given":"Charles","family":"Augustine","sequence":"additional","affiliation":[]},{"given":"Zhengya","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Jim","family":"Tschanz","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Theory of Self-Reproducing Automata","year":"1966","author":"von neumann","key":"17"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1972.1155118"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.73"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1987.1052809"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1080\/15320370108500218"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2009.01.015"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242496"},{"year":"0","key":"12"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775920"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/4.982424"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/4.126534"},{"key":"10","first-page":"458","article-title":"A process-variation-tolerant dual-power-supply SRAM with 179 um2 cell in 40nm CMOS using level-programmable wordline driver","author":"hirabayashi","year":"2009","journal-title":"ISSCC"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382599"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2004.1283650"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609436"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/16.848285"},{"key":"9","first-page":"230","article-title":"A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry","author":"karl","year":"2012","journal-title":"ISSCC"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.891648"}],"event":{"name":"2013 IEEE International Symposium on Low Power Electronics and Design (ISLPED)","start":{"date-parts":[[2013,9,4]]},"location":"Beijing, China","end":{"date-parts":[[2013,9,6]]}},"container-title":["International Symposium on Low Power Electronics and Design (ISLPED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6613639\/6629247\/06629291.pdf?arnumber=6629291","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T03:19:27Z","timestamp":1490239167000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6629291\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,9]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/islped.2013.6629291","relation":{},"subject":[],"published":{"date-parts":[[2013,9]]}}}