{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T20:31:11Z","timestamp":1725395471666},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,9]]},"DOI":"10.1109\/islped.2013.6629294","type":"proceedings-article","created":{"date-parts":[[2013,12,17]],"date-time":"2013-12-17T20:47:27Z","timestamp":1387313247000},"page":"199-204","source":"Crossref","is-referenced-by-count":9,"title":["A pipeline architecture with 1-cycle timing error correction for low voltage operations"],"prefix":"10.1109","author":[{"given":"Insup","family":"Shin","sequence":"first","affiliation":[]},{"given":"Jae-Joon","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Yu-Shiang","family":"Lin","sequence":"additional","affiliation":[]},{"given":"Youngsoo","family":"Shin","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"year":"0","key":"13"},{"year":"0","key":"11"},{"year":"0","key":"12"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373409"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.825120"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6177103"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2089657"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2004.85"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"5","first-page":"112","article-title":"Tunable replica circuits and adaptive voltagefrequency techniques for dynamic voltage, temperature, and aging variation tolerance","author":"tschanz","year":"2009","journal-title":"Proc Symp on VLSI Circuits"},{"key":"4","first-page":"398","article-title":"A distributed critical-path timing monitor for a 65 nm high-performance microprocessor","author":"drake","year":"2007","journal-title":"Proc Int Solid-State Circuits Conf"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007148"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007145"}],"event":{"name":"2013 IEEE International Symposium on Low Power Electronics and Design (ISLPED)","start":{"date-parts":[[2013,9,4]]},"location":"Beijing, China","end":{"date-parts":[[2013,9,6]]}},"container-title":["International Symposium on Low Power Electronics and Design (ISLPED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6613639\/6629247\/06629294.pdf?arnumber=6629294","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T03:22:52Z","timestamp":1490239372000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6629294\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,9]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/islped.2013.6629294","relation":{},"subject":[],"published":{"date-parts":[[2013,9]]}}}