{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T19:23:14Z","timestamp":1725736994859},"reference-count":29,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,9]]},"DOI":"10.1109\/islped.2013.6629312","type":"proceedings-article","created":{"date-parts":[[2013,12,17]],"date-time":"2013-12-17T15:47:27Z","timestamp":1387295247000},"page":"298-303","source":"Crossref","is-referenced-by-count":10,"title":["Page policy control with memory partitioning for DRAM performance and power efficiency"],"prefix":"10.1109","author":[{"given":"Mingli","family":"Xie","sequence":"first","affiliation":[]},{"given":"Dong","family":"Tong","sequence":"additional","affiliation":[]},{"given":"Yi","family":"Feng","sequence":"additional","affiliation":[]},{"given":"Kan","family":"Huang","sequence":"additional","affiliation":[]},{"given":"Xu","family":"Cheng","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.108"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155664"},{"key":"15","article-title":"Software-hardware cooperative dram bank partitioning for chip multiprocessors","author":"mi","year":"2010","journal-title":"NPC"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6168944"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.7"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.24"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.51"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.21"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2005.195553"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2011.31"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379007"},{"key":"24","doi-asserted-by":"crossref","first-page":"37","DOI":"10.1145\/344166.344189","article-title":"operating-system directed power reduction","author":"lu","year":"2000","journal-title":"ISLPED 00 the 2000 International Symposium on Low Power Electronics and Design (Cat No 00TH8514) LPE-00"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1145\/1024393.1024415"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370869"},{"key":"27","article-title":"RAMZzz: Rank-aware dram power management with dynamic migrations and demotions","author":"wu","year":"2012","journal-title":"SC"},{"key":"28","article-title":"History-based memory mode prediction for improving memory performance","author":"park","year":"2003","journal-title":"ISCAS"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228517"},{"year":"0","key":"3"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237047"},{"key":"10","article-title":"ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers","author":"kim","year":"2010","journal-title":"HPCA"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250699"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1250880"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771792"},{"key":"5","first-page":"128","article-title":"Memory access scheduling","author":"rixner","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"year":"0","key":"4"},{"journal-title":"Memory Systems Cache","year":"2008","author":"jacob","key":"9"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155624"}],"event":{"name":"2013 IEEE International Symposium on Low Power Electronics and Design (ISLPED)","start":{"date-parts":[[2013,9,4]]},"location":"Beijing, China","end":{"date-parts":[[2013,9,6]]}},"container-title":["International Symposium on Low Power Electronics and Design (ISLPED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6613639\/6629247\/06629312.pdf?arnumber=6629312","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T00:25:24Z","timestamp":1498091124000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6629312\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,9]]},"references-count":29,"URL":"https:\/\/doi.org\/10.1109\/islped.2013.6629312","relation":{},"subject":[],"published":{"date-parts":[[2013,9]]}}}