{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,15]],"date-time":"2026-01-15T02:16:26Z","timestamp":1768443386455,"version":"3.49.0"},"reference-count":26,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,7]]},"DOI":"10.1109\/islped.2017.8009157","type":"proceedings-article","created":{"date-parts":[[2017,8,14]],"date-time":"2017-08-14T20:31:31Z","timestamp":1502742691000},"page":"1-6","source":"Crossref","is-referenced-by-count":16,"title":["Architecting large-scale SRAM arrays with monolithic 3D integration"],"prefix":"10.1109","author":[{"given":"Joonho","family":"Kong","sequence":"first","affiliation":[]},{"given":"Young-Ho","family":"Gong","sequence":"additional","affiliation":[]},{"given":"Sung Woo","family":"Chung","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2014.2378291"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2010.5490828"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2012.6187545"},{"key":"ref14","author":"muralimanohar","year":"0","journal-title":"CACTI 6 0 A Tool to Model Large Caches"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2008.4672058"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837312"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593188"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346197"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.92"},{"key":"ref4","article-title":"CACTI-3DD: Architecture-level Modeling for 3D Die-Stacked DRAM Main Memory","author":"chen","year":"0","journal-title":"DATE 2012"},{"key":"ref3","article-title":"Technology Comparison for Large Last-level Caches (L3Cs): Low-leakage SRAM, Low Write-energy STT-RAM, and Refresh-optimized eDRAM","author":"chang","year":"0","journal-title":"HPCA 2013"},{"key":"ref6","year":"2013","journal-title":"ITRS International Technology Roadmap for Semiconductors"},{"key":"ref5","year":"0","journal-title":"Intel XEON processor E7–8893 v4 processor specifications"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749757"},{"key":"ref7","year":"2013","journal-title":"JEDEC Standard High Bandwidth Memory(HBM) DRAM Specification"},{"key":"ref2","doi-asserted-by":"crossref","DOI":"10.1145\/2024716.2024718","article-title":"The Gem5 Simulator","volume":"39","author":"binkert","year":"2011","journal-title":"SIGARCH Comput Archit News"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2187671.2187675"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5654245"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.891300"},{"key":"ref22","article-title":"Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3D ICs","author":"samal","year":"2016","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593140"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2016.94"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2934583.2934643"},{"key":"ref26","article-title":"Improvements in Low Temperature FDSOI Devices Down to 30nm Gate Length","author":"xu","year":"2012","journal-title":"International Symposium on VLSI Technology Systems and Applications"},{"key":"ref25","article-title":"An introduction to POWER8 processor","author":"tendler","year":"2014","journal-title":"IBM Corporation"}],"event":{"name":"2017 IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED)","location":"Taipei, Taiwan","start":{"date-parts":[[2017,7,24]]},"end":{"date-parts":[[2017,7,26]]}},"container-title":["2017 IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8002794\/8009138\/08009157.pdf?arnumber=8009157","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,2]],"date-time":"2019-10-02T11:47:06Z","timestamp":1570016826000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8009157\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,7]]},"references-count":26,"URL":"https:\/\/doi.org\/10.1109\/islped.2017.8009157","relation":{},"subject":[],"published":{"date-parts":[[2017,7]]}}}