{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T23:06:11Z","timestamp":1747868771577},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,7]]},"DOI":"10.1109\/islped.2017.8009173","type":"proceedings-article","created":{"date-parts":[[2017,8,14]],"date-time":"2017-08-14T20:31:31Z","timestamp":1502742691000},"page":"1-6","source":"Crossref","is-referenced-by-count":25,"title":["Approximate memory compression for energy-efficiency"],"prefix":"10.1109","author":[{"given":"Ashish","family":"Ranjan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Arnab","family":"Raha","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vijay","family":"Raghunathan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anand","family":"Raghunathan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744799"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927016"},{"journal-title":"A Primer on Compression in the Memory Hierarchy","year":"2015","author":"sardashti","key":"ref12"},{"key":"ref13","article-title":"Linearly compressed pages: A low-complexity, low-latency main memory compression framework","author":"pekhimnko","year":"0","journal-title":"Microtherm 2013"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2002.998312"},{"journal-title":"Altera NIOS II Processors","year":"2015","key":"ref15"},{"journal-title":"Altera Introduction to UniPHY IP","year":"2013","key":"ref16"},{"key":"ref4","article-title":"Quality Configurable Approximate DRAM","author":"raha","year":"2016","journal-title":"IEEE Transactions on Computers"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950391"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540712"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2016.7428043"},{"key":"ref8","article-title":"Doppelg&#x00E4;nger: A Cache for Approximate Computing","author":"miguel","year":"0","journal-title":"Proc MICRO 2015"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.22"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2751163"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2015.2505723"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783744"}],"event":{"name":"2017 IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED)","start":{"date-parts":[[2017,7,24]]},"location":"Taipei, Taiwan","end":{"date-parts":[[2017,7,26]]}},"container-title":["2017 IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8002794\/8009138\/08009173.pdf?arnumber=8009173","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,12,13]],"date-time":"2017-12-13T20:32:11Z","timestamp":1513197131000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8009173\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,7]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/islped.2017.8009173","relation":{},"subject":[],"published":{"date-parts":[[2017,7]]}}}