{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,22]],"date-time":"2025-05-22T05:49:41Z","timestamp":1747892981154,"version":"3.28.0"},"reference-count":22,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,7]]},"DOI":"10.1109\/islped.2019.8824902","type":"proceedings-article","created":{"date-parts":[[2019,9,5]],"date-time":"2019-09-05T23:11:46Z","timestamp":1567725106000},"page":"1-6","source":"Crossref","is-referenced-by-count":10,"title":["VCAM: Variation Compensation through Activation Matching for Analog Binarized Neural Networks"],"prefix":"10.1109","author":[{"given":"Jaehyun","family":"Kim","sequence":"first","affiliation":[]},{"given":"Chaeun","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Jihun","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Yumin","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Cheol Seong","family":"Hwang","sequence":"additional","affiliation":[]},{"given":"Kiyoung","family":"Choi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/ASPDAC.2017.7858419"},{"key":"ref11","article-title":"An always-on 3.8 &#x00B5;J\/86% CIFAR-10 mixed-signal binary CNN processor with all memory on chip in 28nm CMOS","author":"bankman","year":"2018","journal-title":"Proc ISSCC"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.3390\/make1010005"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/MICRO.2014.58"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1186\/1556-276X-9-526"},{"key":"ref15","article-title":"Dorefa-net: Training low bitwidth convolutional neural networks with low bitwidth gradients","author":"zhou","year":"2016","journal-title":"arXiv preprint arXiv 1606 06160"},{"key":"ref16","article-title":"Batch normalization: Accelerating deep network training by reducing internal covariate shift","author":"ioffe","year":"2015","journal-title":"Proc ICML"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"5698","DOI":"10.1039\/C4NR00500G","article-title":"Multi-level control of conductive nano-filament evolution in hfo 2 reram by pulse-train operations","volume":"6","author":"philip\u00e1wong","year":"2014","journal-title":"Nanoscale"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1561\/1000000031"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1109\/4.982424"},{"key":"ref4","article-title":"Binarized neural networks: Training deep neural networks with weights and activations constrained to +1 or -1","author":"courbariaux","year":"2016","journal-title":"ArXiv"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"529","DOI":"10.1038\/nature14236","article-title":"Human-level control through deep reinforcement learning","volume":"518","author":"mnih","year":"2015","journal-title":"Nature"},{"key":"ref6","article-title":"XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks","author":"sun","year":"2018","journal-title":"Proc DATE"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/FPT.2016.7929192"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/ASPDAC.2018.8297384"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/ISLPED.2017.8009177"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/MSP.2012.2205597"},{"key":"ref1","first-page":"1097","article-title":"Imagenet classification with deep convolutional neural networks","author":"krizhevsky","year":"2012","journal-title":"Advances in neural information processing systems"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/JSSC.2017.2712626"},{"key":"ref20","article-title":"Deep neural networks are robust to weight binarization and other non-linear distortions","author":"merolla","year":"2016","journal-title":"ArXiv"},{"doi-asserted-by":"publisher","key":"ref22","DOI":"10.1109\/TED.2017.2742702"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.1109\/JSSC.2009.2022217"}],"event":{"name":"2019 IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED)","start":{"date-parts":[[2019,7,29]]},"location":"Lausanne, Switzerland","end":{"date-parts":[[2019,7,31]]}},"container-title":["2019 IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8819888\/8824790\/08824902.pdf?arnumber=8824902","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,15]],"date-time":"2022-07-15T03:07:19Z","timestamp":1657854439000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8824902\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,7]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/islped.2019.8824902","relation":{},"subject":[],"published":{"date-parts":[[2019,7]]}}}