{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,15]],"date-time":"2024-08-15T05:13:51Z","timestamp":1723698831996},"reference-count":31,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,7,26]],"date-time":"2021-07-26T00:00:00Z","timestamp":1627257600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,7,26]],"date-time":"2021-07-26T00:00:00Z","timestamp":1627257600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,7,26]],"date-time":"2021-07-26T00:00:00Z","timestamp":1627257600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,7,26]]},"DOI":"10.1109\/islped52811.2021.9502474","type":"proceedings-article","created":{"date-parts":[[2021,8,4]],"date-time":"2021-08-04T20:52:28Z","timestamp":1628110348000},"source":"Crossref","is-referenced-by-count":4,"title":["FPRA: A Fine-grained Parallel RRAM Architecture"],"prefix":"10.1109","author":[{"given":"Xiao","family":"Liu","sequence":"first","affiliation":[]},{"given":"Minxuan","family":"Zhou","sequence":"additional","affiliation":[]},{"given":"Rachata","family":"Ausavarungnirun","sequence":"additional","affiliation":[]},{"given":"Sean","family":"Eilert","sequence":"additional","affiliation":[]},{"given":"Ameen","family":"Akel","sequence":"additional","affiliation":[]},{"given":"Tajana","family":"Rosing","sequence":"additional","affiliation":[]},{"given":"Vijaykrishnan","family":"Narayanan","sequence":"additional","affiliation":[]},{"given":"Jishen","family":"Zhao","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2018.2790840"},{"key":"ref30","year":"2019","journal-title":"torchvision – pytorch master documentation"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898010"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173205"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3297858.3304048"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2414456"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2013.6487818"},{"key":"ref16","article-title":"ShuffleNet V2: Practical guidelines for efficient CNN architecture design","author":"ma","year":"2018","journal-title":"ECCV"},{"key":"ref17","article-title":"CACTI 6.0: A tool to model large caches","author":"muralimanohar","year":"2009","journal-title":"HP Laboratories"},{"key":"ref18","article-title":"PyTorch: An imperative style, high-performance deep learning library","author":"paszke","year":"2019","journal-title":"NIPS"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3195998"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2015.7298594"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2017.2761740"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173177"},{"key":"ref6","article-title":"CASCADE: Connecting rrams to extend analog dataflow in an end-to-end in-memory processing paradigm","author":"chou","year":"2019","journal-title":"Micro"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.308"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001140"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173171"},{"key":"ref7","article-title":"ImageNet: A large-scale hierarchical image database","author":"deng","year":"2018","journal-title":"CVPR"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3297858.3304049"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref1","article-title":"Tensorflow: A system for large-scale machine learning","author":"abadi","year":"2016","journal-title":"OSDI"},{"key":"ref20","article-title":"Glow: Graph lowering compiler techniques for neural networks","author":"rotem","year":"2018"},{"key":"ref22","article-title":"MobileNetV2: Inverted residuals and linear bottle-necks","author":"sandler","year":"2018","journal-title":"CVPR"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2107214"},{"key":"ref24","article-title":"Very deep convolutional networks for large-scale image recognition","author":"simonyan","year":"2014","journal-title":"arXiv preprint arXiv 1409 1556"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001139"},{"key":"ref26","year":"2020","journal-title":"Teaching Resources for IC Design"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.55"}],"event":{"name":"2021 IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED)","location":"Boston, MA, USA","start":{"date-parts":[[2021,7,26]]},"end":{"date-parts":[[2021,7,28]]}},"container-title":["2021 IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9502425\/9502469\/09502474.pdf?arnumber=9502474","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T15:44:22Z","timestamp":1652197462000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9502474\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,7,26]]},"references-count":31,"URL":"https:\/\/doi.org\/10.1109\/islped52811.2021.9502474","relation":{},"subject":[],"published":{"date-parts":[[2021,7,26]]}}}