{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,9]],"date-time":"2026-04-09T10:57:26Z","timestamp":1775732246805,"version":"3.50.1"},"reference-count":29,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,8,7]],"date-time":"2023-08-07T00:00:00Z","timestamp":1691366400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,8,7]],"date-time":"2023-08-07T00:00:00Z","timestamp":1691366400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,8,7]]},"DOI":"10.1109\/islped58423.2023.10244526","type":"proceedings-article","created":{"date-parts":[[2023,9,19]],"date-time":"2023-09-19T17:38:53Z","timestamp":1695145133000},"page":"1-6","source":"Crossref","is-referenced-by-count":7,"title":["FPGA-Patch: Mitigating Remote Side-Channel Attacks on FPGAs using Dynamic Patch Generation"],"prefix":"10.1109","author":[{"given":"Mahya Morid","family":"Ahmadi","sequence":"first","affiliation":[{"name":"Faculty of Informatics Vienna University of Technology (TU Wien),Vienna,Austria"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lilas","family":"Alrahis","sequence":"additional","affiliation":[{"name":"University Abu Dhabi (NYUAD),Division of Engineering New York,Abu Dhabi,United Arab Emirates"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ozgur","family":"Sinanoglu","sequence":"additional","affiliation":[{"name":"University Abu Dhabi (NYUAD),Division of Engineering New York,Abu Dhabi,United Arab Emirates"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Muhammad","family":"Shafique","sequence":"additional","affiliation":[{"name":"University Abu Dhabi (NYUAD),Division of Engineering New York,Abu Dhabi,United Arab Emirates"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2018.00055"},{"key":"ref12","article-title":"Aws ec2 FPGA hdk+sdk errata","year":"2021","journal-title":"Amazon"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375322"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ETS54262.2022.9810438"},{"key":"ref11","first-page":"1","article-title":"ShapeShifter: Protecting FPGAs from side-channel attacks with isofunctional heterogeneous modules","author":"morid ahmadi","year":"2023","journal-title":"IOLTS"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI51109.2021.00059"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2018.00016"},{"key":"ref1","author":"jin","year":"2020","journal-title":"Security of Cloud FPGAs A Survey"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9473938"},{"key":"ref16","first-page":"1","article-title":"Learning malicious circuits in FPGA bitstreams","author":"elnaggar","year":"2022","journal-title":"TCAD"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig48160.2019.8994789"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317899"},{"key":"ref24","author":"krishnegowda","year":"2021","journal-title":"A primer on logical equivalence checking (lec) using conformal"},{"key":"ref23","first-page":"188","article-title":"Moving target and implementation diversity based countermeasures against side-channel attacks","author":"khan","year":"2021","journal-title":"ARC"},{"key":"ref26","author":"villar","year":"2019","journal-title":"Opencores 128\/192 aes"},{"key":"ref25","first-page":"13","volume":"4","author":"bow","year":"2020","journal-title":"Side-channel power resistance for encryption algorithms using implementation diversity"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942094"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-79025-7_12"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8714801"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-28632-5_2"},{"key":"ref27","first-page":"29","article-title":"A fast high-resolution time-to-digital converter implemented in a zynq 7010 soc","author":"adami?","year":"2019","journal-title":"Austrochip"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-79025-7_13"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2018.00049"},{"key":"ref7","article-title":"Voltage sensor implementations for remote power attacks on FPGAs","author":"moini","year":"2022","journal-title":"TRETS"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2019.00039"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2020.i3.121-146"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00031"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8714904"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.3027711"}],"event":{"name":"2023 IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED)","location":"Vienna, Austria","start":{"date-parts":[[2023,8,7]]},"end":{"date-parts":[[2023,8,8]]}},"container-title":["2023 IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10244176\/10244185\/10244526.pdf?arnumber=10244526","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,9]],"date-time":"2023-10-09T17:59:02Z","timestamp":1696874342000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10244526\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,8,7]]},"references-count":29,"URL":"https:\/\/doi.org\/10.1109\/islped58423.2023.10244526","relation":{},"subject":[],"published":{"date-parts":[[2023,8,7]]}}}