{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,11]],"date-time":"2025-11-11T13:52:56Z","timestamp":1762869176209},"reference-count":14,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,8,7]],"date-time":"2023-08-07T00:00:00Z","timestamp":1691366400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,8,7]],"date-time":"2023-08-07T00:00:00Z","timestamp":1691366400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,8,7]]},"DOI":"10.1109\/islped58423.2023.10244724","type":"proceedings-article","created":{"date-parts":[[2023,9,19]],"date-time":"2023-09-19T17:38:53Z","timestamp":1695145133000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Cryogenic CMOS as an Enabler for Low Power Dynamic Logic"],"prefix":"10.1109","author":[{"given":"Rakshith","family":"Saligram","sequence":"first","affiliation":[{"name":"School of Electrical & Computer Engineering Georgia Institute of Technology,Atlanta,USA"}]},{"given":"Suman","family":"Datta","sequence":"additional","affiliation":[{"name":"School of Electrical & Computer Engineering Georgia Institute of Technology,Atlanta,USA"}]},{"given":"Arijit","family":"Raychowdhury","sequence":"additional","affiliation":[{"name":"School of Electrical & Computer Engineering Georgia Institute of Technology,Atlanta,USA"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnology18217.2020.9265065"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/CICC51472.2021.9431559"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2019.2963379"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2021.3117277"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-021-03469-4"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/nssmic.2009.5401690"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1103\/RevModPhys.89.035002"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2006.05.010"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2007.905092"},{"key":"ref10","first-page":"2","article-title":"22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications","author":"Carteret","year":"2016","journal-title":"inIEDM Tech. Dig."},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JXCDC.2021.3131100"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1147\/rd.252.0156"},{"key":"ref13","first-page":"362","article-title":"A Sub-Nanosecond 0.5\u03bcm 64b Adder Design","author":"Naffziger","year":"1996","journal-title":"ISSCC Dig. Tech. Papers"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2006.1696230"}],"event":{"name":"2023 IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED)","start":{"date-parts":[[2023,8,7]]},"location":"Vienna, Austria","end":{"date-parts":[[2023,8,8]]}},"container-title":["2023 IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10244176\/10244185\/10244724.pdf?arnumber=10244724","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,3,2]],"date-time":"2024-03-02T00:41:20Z","timestamp":1709340080000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10244724\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,8,7]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/islped58423.2023.10244724","relation":{},"subject":[],"published":{"date-parts":[[2023,8,7]]}}}