{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T20:38:40Z","timestamp":1729629520569,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/ismvl.2002.1011091","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T20:42:54Z","timestamp":1056573774000},"page":"209-215","source":"Crossref","is-referenced-by-count":0,"title":["The word-level models for efficient computation of multiple-valued functions.2. LWL based model"],"prefix":"10.1109","author":[{"given":"A.M.","family":"Tomaszewska","sequence":"first","affiliation":[]},{"given":"S.N.","family":"Yanushkevich","sequence":"additional","affiliation":[]},{"given":"V.P.","family":"Shmerko","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/FTCS.1990.89336"},{"year":"0","author":"feinberg","journal-title":"VLSI Planarization Methods Models Implementation","key":"ref3"},{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/ISMVL.1999.779692"},{"key":"ref6","first-page":"141","article-title":"On Minimization of Multiple-Valued Sum-of-Products Expression with Multiple-Valued TRSUM","volume":"2","author":"hozumi","year":"1997","journal-title":"Multiple-Valued Logic - An International Journal"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/ISMVL.1993.289560"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/ISMVL.1993.289585"},{"key":"ref12","doi-asserted-by":"crossref","DOI":"10.1109\/ISMVL.2002.1011090","article-title":"The Word-Level Models for Efficient Computation of Multiple-Valued Functions, PART 1","author":"yanushkevich","year":"2002","journal-title":"LAR Based Model Proc 32nd IEEE Int Symp on lvlultiple-Valued Logic"},{"key":"ref8","article-title":"Parallel Calculation by Means of Arythmetical Polynomials","author":"malyugin","year":"1997","journal-title":"Physical and Mathematical Publishing Company"},{"year":"1991","author":"kukharev","journal-title":"Parallel Processing of Binary Data in VLSI","key":"ref7"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/72.728356"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1007\/BF02478259"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1007\/978-1-4615-3958-2"}],"event":{"acronym":"ISMVL-02","name":"32nd IEEE International Symposium on Multi-Valued Logic","location":"Boston, MA, USA"},"container-title":["Proceedings 32nd IEEE International Symposium on Multiple- Valued Logic"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/7900\/21788\/01011091.pdf?arnumber=1011091","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T22:40:42Z","timestamp":1497566442000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1011091\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/ismvl.2002.1011091","relation":{},"subject":[]}}