{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T20:23:51Z","timestamp":1729628631482,"version":"3.28.0"},"reference-count":25,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/ismvl.2002.1011097","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T16:42:54Z","timestamp":1056559374000},"page":"261-267","source":"Crossref","is-referenced-by-count":4,"title":["Representations of logic functions using QRMDDs"],"prefix":"10.1109","author":[{"given":"S.","family":"Nagayama","sequence":"first","affiliation":[]},{"given":"T.","family":"Sasao","sequence":"additional","affiliation":[]},{"given":"Y.","family":"Iguchi","sequence":"additional","affiliation":[]},{"given":"M.","family":"Matsuura","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"9","article-title":"Multi-valued decision diagrams: Theory and Applications","volume":"4","author":"kam","year":"1998","journal-title":"Multiple-Valued Logic 1988"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/12.144618"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1995.480147"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1990.114828"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISMVL.1993.289589"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1993.580030"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"413","DOI":"10.1145\/127601.127704","article-title":"Breadth-first manipulation of SBDD of boolean functions for vector processing","author":"ochi","year":"1991","journal-title":"28th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref17","first-page":"233","article-title":"FPGA design by generalized functional decomposition","author":"sasao","year":"1993"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4613-1385-4"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISMVL.1996.508365"},{"key":"ref4","first-page":"408","article-title":"The future of logic synthesis and verification","author":"brayton","year":"2001"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISMVL.1994.302218"},{"key":"ref6","first-page":"663","article-title":"Neutral netlist of ten combinational benchmark circuits and a target translator in FORTRAN","author":"brglez","year":"1985","journal-title":"Special session on ATPG and fault simulation Proc IEEE Int Symp Circuits and Systems"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/322261.322269"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2000.835073"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1986.1676819"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/43.766731"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISMVL.2000.848620"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1995.480148"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5139-3"},{"key":"ref22","first-page":"225","article-title":"Cascade realization of multiple-output function and its application to reconfigurable hardware","author":"sasao","year":"2001","journal-title":"International Workshop on Logic and Synthesis"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISMVL.2001.924574"},{"key":"ref24","doi-asserted-by":"crossref","DOI":"10.1137\/1.9780898719789","author":"wegener","year":"0","journal-title":"Branching Programs and Binary Decision Diagrams Theory and Applications"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/800135.804401"},{"key":"ref25","article-title":"Logic synthesis and optimization benchmark user guide version 3.0","author":"yang","year":"1991","journal-title":"MCNC"}],"event":{"name":"32nd IEEE International Symposium on Multi-Valued Logic","acronym":"ISMVL-02","location":"Boston, MA, USA"},"container-title":["Proceedings 32nd IEEE International Symposium on Multiple- Valued Logic"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/7900\/21788\/01011097.pdf?arnumber=1011097","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T18:40:43Z","timestamp":1497552043000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1011097\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/ismvl.2002.1011097","relation":{},"subject":[]}}