{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T03:19:41Z","timestamp":1729653581289,"version":"3.28.0"},"reference-count":9,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/ismvl.2002.1011100","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T16:42:54Z","timestamp":1056559374000},"page":"282-288","source":"Crossref","is-referenced-by-count":11,"title":["Multi-valued flip-flop with neuron-CMOS NMIN circuits"],"prefix":"10.1109","author":[{"given":"M.","family":"Inaba","sequence":"first","affiliation":[]},{"given":"K.","family":"Tanno","sequence":"additional","affiliation":[]},{"given":"O.","family":"Ishizuka","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","article-title":"Analog Inverter with Neuron-MOS Transistors and Its Application","author":"motoi","year":"0","journal-title":"Kluwer's International Journal"},{"key":"ref3","article-title":"Voltage-Mode Variable Threshold Circuits with Neuron MOS Transistors for Multi-Valued Logic","author":"inaba","year":"0","journal-title":"International Journal Special Issue on Dreams of Innovative MVL Researches"},{"article-title":"Multiple-Valued Digital Processing System","year":"1989","author":"higuchi","key":"ref6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISMVL.2001.924551"},{"key":"ref8","article-title":"Circuit Design of a Ternary Flip-Flop Using Ternary Logic Gates","author":"young-hee","year":"2001","journal-title":"The Second Korea-Japan Joint Symposium on Multiple-Valued Logic"},{"key":"ref7","first-page":"149","article-title":"Multiple Valued Logic Static Latch Circuits","volume":"7","author":"current","year":"2001","journal-title":"Multiple-Valued Logic - An International Journal"},{"key":"ref2","doi-asserted-by":"crossref","DOI":"10.1109\/ISMVL.1999.779714","article-title":"Down Literal Circuit with Neuron-MOS Transistors and Its Applications","author":"shen","year":"1999","journal-title":"29th International Symposium on Multiple-Valued Logic (ISMVL'99)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISMVL.2001.924559"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/16.137325"}],"event":{"name":"32nd IEEE International Symposium on Multi-Valued Logic","acronym":"ISMVL-02","location":"Boston, MA, USA"},"container-title":["Proceedings 32nd IEEE International Symposium on Multiple- Valued Logic"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/7900\/21788\/01011100.pdf?arnumber=1011100","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T18:40:43Z","timestamp":1497552043000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1011100\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/ismvl.2002.1011100","relation":{},"subject":[]}}