{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T07:56:58Z","timestamp":1730275018895,"version":"3.28.0"},"reference-count":9,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/ismvl.2004.1319932","type":"proceedings-article","created":{"date-parts":[[2004,9,28]],"date-time":"2004-09-28T09:50:22Z","timestamp":1096365022000},"page":"135-140","source":"Crossref","is-referenced-by-count":0,"title":["A systolic parallel multiplier over GF(3\/sup m\/) using neuron-MOS DLC [down-literal circuit]"],"prefix":"10.1109","author":[{"family":"Byoung Hee Yoon","sequence":"first","affiliation":[]},{"family":"Sung Il Han","sequence":"additional","affiliation":[]},{"family":"Young-Hee Choi","sequence":"additional","affiliation":[]},{"family":"Jong-Hak Hwang","sequence":"additional","affiliation":[]},{"family":"Hyeon-Kyeong Seong","sequence":"additional","affiliation":[]},{"family":"Heung Soo Kim","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","first-page":"297","article-title":"VLSI Architectures for Multiplication Over Finite Field GF(2m)","author":"mastrovito","year":"1988","journal-title":"Applied Algebraic Algorithms and Error-Correcting Code Proc Sixth Int'l Conf AAECC-6"},{"key":"ref3","article-title":"A fast multiplier for GF(2m)","volume":"sac 4","author":"scott","year":"1986","journal-title":"IEEE J Select Areas Commun"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/12.769434"},{"article-title":"VLSI Architectures for Computation in Galois Fields","year":"1991","author":"mastrovito","key":"ref5"},{"key":"ref8","first-page":"180","article-title":"A Ternary Systolic Product-Sum Circuit for GF(3m) using Neuron MOSFETs","author":"muranaka","year":"1999","journal-title":"Proc 29th ISMVL"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/12.926154"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1984.1676441"},{"key":"ref9","first-page":"180","article-title":"Down Literal circuit with Neuron-MOS Transistors and Its Applications","author":"shen","year":"1999","journal-title":"Proc 29th ISMVL"},{"key":"ref1","first-page":"1161","article-title":"Multiple-valued logic-its future","volume":"30","author":"hurst","year":"1984","journal-title":"IEEE Trans Computers"}],"event":{"name":"Proceedings. 34th International Symposium on Multiple-Valued Logic","acronym":"ISMVL-04","location":"Toronto, Ont., Canada"},"container-title":["Proceedings. 34th International Symposium on Multiple-Valued Logic"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9226\/29244\/01319932.pdf?arnumber=1319932","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,14]],"date-time":"2017-03-14T22:49:54Z","timestamp":1489531794000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1319932\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/ismvl.2004.1319932","relation":{},"subject":[]}}