{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,12]],"date-time":"2026-06-12T06:59:54Z","timestamp":1781247594514,"version":"3.54.1"},"reference-count":11,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,5,19]],"date-time":"2026-05-19T00:00:00Z","timestamp":1779148800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,5,19]],"date-time":"2026-05-19T00:00:00Z","timestamp":1779148800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,5,19]]},"DOI":"10.1109\/ismvl68998.2026.00044","type":"proceedings-article","created":{"date-parts":[[2026,6,11]],"date-time":"2026-06-11T19:58:49Z","timestamp":1781207929000},"page":"204-209","source":"Crossref","is-referenced-by-count":0,"title":["Minimization of Reversible Logic Circuits Using A* with Lookahead"],"prefix":"10.1109","author":[{"given":"Hyunsu","family":"Choi","sequence":"first","affiliation":[{"name":"Iwate University,Computer Science and Intelligent Systems,Morioka,Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Takashi","family":"Hirayama","sequence":"additional","affiliation":[{"name":"Iwate University,Computer Science and Intelligent Systems,Morioka,Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Katsuhisa","family":"Yamanaka","sequence":"additional","affiliation":[{"name":"Iwate University,Computer Science and Intelligent Systems,Morioka,Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-90-481-9579-4"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2431211.2431220"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.21236\/ADA082021"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.811448"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2017215"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837440"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.26421\/QIC8.3-4-4"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3828.3830"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TSSC.1968.300136"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1609\/aaai.v24i1.7559"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1587\/transinf.2023LOP0003"}],"event":{"name":"2026 IEEE 56th International Symposium on Multiple-Valued Logic (ISMVL)","location":"Sendai, Japan","start":{"date-parts":[[2026,5,19]]},"end":{"date-parts":[[2026,5,21]]}},"container-title":["2026 IEEE 56th International Symposium on Multiple-Valued Logic (ISMVL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11555011\/11555977\/11556003.pdf?arnumber=11556003","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,12]],"date-time":"2026-06-12T06:21:59Z","timestamp":1781245319000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11556003\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,5,19]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/ismvl68998.2026.00044","relation":{},"subject":[],"published":{"date-parts":[[2026,5,19]]}}}