{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T00:22:51Z","timestamp":1729642971793,"version":"3.28.0"},"reference-count":35,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,11]]},"DOI":"10.1109\/isocc.2012.6407071","type":"proceedings-article","created":{"date-parts":[[2013,1,17]],"date-time":"2013-01-17T20:36:38Z","timestamp":1358454998000},"page":"188-191","source":"Crossref","is-referenced-by-count":0,"title":["Error Injection &amp;amp; Correction: An efficient formal logic restructuring algorithm"],"prefix":"10.1109","author":[{"family":"Ching-Yi Huang","sequence":"first","affiliation":[]},{"family":"Daw-Ming Lee","sequence":"additional","affiliation":[]},{"family":"Chun-Chi Lin","sequence":"additional","affiliation":[]},{"family":"Chun-Yao Wang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","first-page":"324","article-title":"Rewiring using IRredundancy removal and addition","author":"lin","year":"2009","journal-title":"Proc DATE"},{"year":"0","key":"35"},{"key":"17","doi-asserted-by":"crossref","first-page":"502","DOI":"10.1145\/37888.37963","article-title":"a topological search algorithm for atpg","author":"kirkland","year":"1987","journal-title":"24th ACM\/IEEE Design Automation Conference"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382542"},{"key":"33","first-page":"1573","article-title":"Almost every wire is removable: A modeling and solution for removing any circuit wire","author":"yang","year":"2012","journal-title":"Proc DATE"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2167327"},{"key":"34","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2006.229206"},{"key":"16","first-page":"197","article-title":"On improved scheme for digital circuit rewiring and application on further improving FPGA technology mapping","author":"fu","year":"2009","journal-title":"Proc ASPDAC"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837399"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2058510"},{"key":"11","first-page":"711","article-title":"An improved approach for alternative wires identification","volume":"2005","author":"chen","year":"2005","journal-title":"Proceedings - IEEE International Conference on Computer Design VLSI in Computers and Processors"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687545"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2006.229287"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/VDAT.2006.258153"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2006.320087"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.358021"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/ICASIC.2003.1277533"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041764"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2001.913354"},{"key":"27","first-page":"104","article-title":"Automatic interconnection rectification for SoC design verification based on the port order fault model","volume":"22","author":"wang","year":"2003","journal-title":"IEEE TCAD"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1109\/43.992770"},{"key":"29","first-page":"259","article-title":"An AVPG for SOC design verification with port order fault model","volume":"5","author":"wang","year":"2001","journal-title":"Proceedings - IEEE International Symposium on Circuits and Systems"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.870836"},{"journal-title":"ABC A System for Sequential Synthesis and Verification","year":"0","key":"2"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/12.795224"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/43.3141"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.917397"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/43.640617"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.814239"},{"key":"32","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837400"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1016\/j.mee.2006.02.017"},{"key":"31","first-page":"268","article-title":"A fast graph-based alternative wiring scheme for boolean networks","author":"wu","year":"2000","journal-title":"Proc Int VLSI Design Conf"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391605"},{"key":"9","first-page":"262","article-title":"Fast boolean optimization by rewiring","author":"chang","year":"1996","journal-title":"Proc ICCAD"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/43.552082"}],"event":{"name":"2012 International SoC Design Conference (ISOCC 2012)","start":{"date-parts":[[2012,11,4]]},"location":"Jeju Island, Korea (South)","end":{"date-parts":[[2012,11,7]]}},"container-title":["2012 International SoC Design Conference (ISOCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6395852\/6406249\/06407071.pdf?arnumber=6407071","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T05:51:25Z","timestamp":1498024285000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6407071\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,11]]},"references-count":35,"URL":"https:\/\/doi.org\/10.1109\/isocc.2012.6407071","relation":{},"subject":[],"published":{"date-parts":[[2012,11]]}}}