{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T06:07:19Z","timestamp":1725430039333},"reference-count":6,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,10]]},"DOI":"10.1109\/isocc.2016.7799709","type":"proceedings-article","created":{"date-parts":[[2016,12,29]],"date-time":"2016-12-29T16:50:06Z","timestamp":1483030206000},"page":"63-64","source":"Crossref","is-referenced-by-count":0,"title":["All-synthesizable transmitter driver and data recovery circuit for USB2.0 interface"],"prefix":"10.1109","author":[{"given":"Kihwan","family":"Seong","sequence":"first","affiliation":[]},{"given":"Won-Cheol","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Byungsub","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Jae-Yoon","family":"Sim","sequence":"additional","affiliation":[]},{"given":"Hong-June","family":"Park","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.5573\/JSTS.2016.16.3.352"},{"key":"ref3","first-page":"285","article-title":"A 0.011 mm2 PVT-Robust Fully-Synthesizable CDR with a Data Rate of 10.05 Gb\/s in 28nm FD SOI","author":"narayanan","year":"2014","journal-title":"IEEE Asian Solid-State Circuits Conference (ASSCC)"},{"key":"ref6","first-page":"156","article-title":"A Single-Data-Bit Blind Oversampling Data-Recovery Circuit With an Add-Drop FIFO for USB2.0 High-Speed Interface","author":"park","year":"2008","journal-title":"IEEE Transaction on circuits and system II (TCAS II)"},{"journal-title":"Intel Hillsboro OR","article-title":"USB2.0 Transceiver Macrocell Interface Specification, Revision 1.05","year":"2001","key":"ref5"},{"key":"ref2","first-page":"250","article-title":"A 0.032 mm2 3.1 mW Synthesized Pixel Clock Generator with 30 psrms Integrated Jitter and 10-to-630MHz DCO Tuning Range","author":"kim","year":"2013","journal-title":"IEEE International Solid-State Circuits Conference (ISSCC)"},{"key":"ref1","first-page":"266","article-title":"A 0.0066 mm2 780 &#x00B5;W Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-Coupled Oscillator Using Edge-Injection Technique","author":"deng","year":"2014","journal-title":"IEEE International Solid-State Circuits Conference (ISSCC)"}],"event":{"name":"2016 International SoC Design Conference (ISOCC)","start":{"date-parts":[[2016,10,23]]},"location":"Jeju, South Korea","end":{"date-parts":[[2016,10,26]]}},"container-title":["2016 International SoC Design Conference (ISOCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7787093\/7799693\/07799709.pdf?arnumber=7799709","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,1,20]],"date-time":"2017-01-20T07:31:41Z","timestamp":1484897501000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7799709\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,10]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/isocc.2016.7799709","relation":{},"subject":[],"published":{"date-parts":[[2016,10]]}}}