{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,21]],"date-time":"2025-08-21T18:01:04Z","timestamp":1755799264032,"version":"3.44.0"},"reference-count":6,"publisher":"IEEE","license":[{"start":{"date-parts":[[2017,11,1]],"date-time":"2017-11-01T00:00:00Z","timestamp":1509494400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2017,11,1]],"date-time":"2017-11-01T00:00:00Z","timestamp":1509494400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,11]]},"DOI":"10.1109\/isocc.2017.8368809","type":"proceedings-article","created":{"date-parts":[[2018,6,22]],"date-time":"2018-06-22T18:04:36Z","timestamp":1529690676000},"page":"21-22","source":"Crossref","is-referenced-by-count":0,"title":["Low-power null convention logic design based on modified gate diffusion input technique"],"prefix":"10.1109","author":[{"given":"Prashanthi","family":"Metku","sequence":"first","affiliation":[{"name":"Dept of ECE, Missouri Univ of Science & Technology, Rolla, MO, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ramu","family":"Seva","sequence":"additional","affiliation":[{"name":"Dept of ECE, Missouri Univ of Science & Technology, Rolla, MO, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kyung Ki","family":"Kim","sequence":"additional","affiliation":[{"name":"Dept of Electronic Eng., Daegu University, Gyeongsan, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yong-Bin","family":"Kim","sequence":"additional","affiliation":[{"name":"Dept of ECE, Northeastern University, Boston, MA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Minsu","family":"Choi","sequence":"additional","affiliation":[{"name":"Dept of ECE, Missouri Univ of Science & Technology, Rolla, MO, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Gate and throughput optimizations for null convention self-timed digital circuits","year":"2001","author":"smith","key":"ref4"},{"key":"ref3","first-page":"13","article-title":"Asynchronous circuit design using new high speed nc1 gates","author":"choi","year":"2014","journal-title":"Proc Int SoC Design Conf (ISOCC)"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.2001.954670"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/EEEI.2010.5662107"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2003.12.004"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.mee.2006.02.012"}],"event":{"name":"2017 International SoC Design Conference (ISOCC)","start":{"date-parts":[[2017,11,5]]},"location":"Seoul, Korea (South)","end":{"date-parts":[[2017,11,8]]}},"container-title":["2017 International SoC Design Conference (ISOCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8362894\/8368771\/08368809.pdf?arnumber=8368809","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,19]],"date-time":"2025-08-19T18:08:46Z","timestamp":1755626926000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8368809\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,11]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/isocc.2017.8368809","relation":{},"subject":[],"published":{"date-parts":[[2017,11]]}}}