{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,21]],"date-time":"2025-08-21T18:01:47Z","timestamp":1755799307753,"version":"3.44.0"},"reference-count":4,"publisher":"IEEE","license":[{"start":{"date-parts":[[2017,11,1]],"date-time":"2017-11-01T00:00:00Z","timestamp":1509494400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2017,11,1]],"date-time":"2017-11-01T00:00:00Z","timestamp":1509494400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,11]]},"DOI":"10.1109\/isocc.2017.8368843","type":"proceedings-article","created":{"date-parts":[[2018,6,22]],"date-time":"2018-06-22T18:04:36Z","timestamp":1529690676000},"page":"155-156","source":"Crossref","is-referenced-by-count":0,"title":["Scalable deep neural network accelerator cores with cubic integration using through chip interface"],"prefix":"10.1109","author":[{"given":"Ryuichi","family":"Sakamoto","sequence":"first","affiliation":[{"name":"Graduate School of Information Science and Technology, The University of Tokyo, Bunkyo-ku, Japan"}]},{"given":"Ryo","family":"Takata","sequence":"additional","affiliation":[{"name":"Graduate School of Information Science and Technology, The University of Tokyo, Bunkyo-ku, Japan"}]},{"given":"Jun","family":"Ishii","sequence":"additional","affiliation":[{"name":"Graduate School of Information Science and Technology, The University of Tokyo, Bunkyo-ku, Japan"}]},{"given":"Masaaki","family":"Kondo","sequence":"additional","affiliation":[{"name":"Graduate School of Information Science and Technology, The University of Tokyo, Bunkyo-ku, Japan"}]},{"given":"Hiroshi","family":"Nakamura","sequence":"additional","affiliation":[{"name":"Graduate School of Information Science and Technology, The University of Tokyo, Bunkyo-ku, Japan"}]},{"given":"Tetsui","family":"Ohkubo","sequence":"additional","affiliation":[{"name":"Department of Information and Computer Science, Keio University, Yokohama, Japan"}]},{"given":"Takuya","family":"Kojima","sequence":"additional","affiliation":[{"name":"Department of Information and Computer Science, Keio University, Yokohama, Japan"}]},{"given":"Hideharu","family":"Amano","sequence":"additional","affiliation":[{"name":"Department of Information and Computer Science, Keio University, Yokohama, Japan"}]}],"member":"263","reference":[{"key":"ref4","article-title":"Deep compression: Compressing deep neural network with pruning, trained quantization and huffman coding","volume":"2","author":"han","year":"2015","journal-title":"CoRR abs\/1510 00149"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001163"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7418007"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.58"}],"event":{"name":"2017 International SoC Design Conference (ISOCC)","start":{"date-parts":[[2017,11,5]]},"location":"Seoul, Korea (South)","end":{"date-parts":[[2017,11,8]]}},"container-title":["2017 International SoC Design Conference (ISOCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8362894\/8368771\/08368843.pdf?arnumber=8368843","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,19]],"date-time":"2025-08-19T18:08:37Z","timestamp":1755626917000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8368843\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,11]]},"references-count":4,"URL":"https:\/\/doi.org\/10.1109\/isocc.2017.8368843","relation":{},"subject":[],"published":{"date-parts":[[2017,11]]}}}