{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T08:06:37Z","timestamp":1730275597686,"version":"3.28.0"},"reference-count":3,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,10,6]],"date-time":"2019-10-06T00:00:00Z","timestamp":1570320000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,10,6]],"date-time":"2019-10-06T00:00:00Z","timestamp":1570320000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,10,6]],"date-time":"2019-10-06T00:00:00Z","timestamp":1570320000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,10,6]]},"DOI":"10.1109\/isocc47750.2019.9027690","type":"proceedings-article","created":{"date-parts":[[2020,3,10]],"date-time":"2020-03-10T06:18:55Z","timestamp":1583821135000},"page":"46-47","source":"Crossref","is-referenced-by-count":0,"title":["Optimization Technique of Memory Traffic for FPGA-Based Image Processing System"],"prefix":"10.1109","author":[{"given":"Kenta","family":"Nishiguchi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Toshiyuki","family":"Inoue","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Akira","family":"Tsuchiya","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kazunori","family":"Ogohara","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Keiji","family":"Kishine","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065729"},{"key":"ref2","first-page":"-8a","article-title":"FPGA-based image processing system with I\/O interface","author":"nishiguchi","year":"0","journal-title":"Proc Society Conf IEICE &#x2018;18"},{"key":"ref1","first-page":"1","article-title":"Towards internet of things: Survey and future vision","volume":"5","author":"said","year":"2013","journal-title":"The International Journal on Computer Networks"}],"event":{"name":"2019 International SoC Design Conference (ISOCC)","start":{"date-parts":[[2019,10,6]]},"location":"Jeju, Korea (South)","end":{"date-parts":[[2019,10,9]]}},"container-title":["2019 International SoC Design Conference (ISOCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9017212\/9027628\/09027690.pdf?arnumber=9027690","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,17]],"date-time":"2022-07-17T21:54:07Z","timestamp":1658094847000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9027690\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,10,6]]},"references-count":3,"URL":"https:\/\/doi.org\/10.1109\/isocc47750.2019.9027690","relation":{},"subject":[],"published":{"date-parts":[[2019,10,6]]}}}