{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,30]],"date-time":"2026-01-30T05:30:57Z","timestamp":1769751057819,"version":"3.49.0"},"reference-count":5,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,10,21]],"date-time":"2020-10-21T00:00:00Z","timestamp":1603238400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,10,21]],"date-time":"2020-10-21T00:00:00Z","timestamp":1603238400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100003725","name":"National Research Foundation of Korea (NRF)","doi-asserted-by":"publisher","award":["NRF-2019M3F3A1A01074449"],"award-info":[{"award-number":["NRF-2019M3F3A1A01074449"]}],"id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,10,21]]},"DOI":"10.1109\/isocc50952.2020.9333036","type":"proceedings-article","created":{"date-parts":[[2021,2,2]],"date-time":"2021-02-02T15:51:49Z","timestamp":1612281109000},"page":"97-98","source":"Crossref","is-referenced-by-count":3,"title":["Extraction of ROM Data from Bitstream in Xilinx FPGA"],"prefix":"10.1109","author":[{"given":"Soyeon","family":"Choi","sequence":"first","affiliation":[{"name":"Chungnam National University,Dept. of Electronics Engineering,Daejeon,South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jieun","family":"Yeo","sequence":"additional","affiliation":[{"name":"Chungnam National University,Dept. of Electronics Engineering,Daejeon,South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hoyoung","family":"Yoo","sequence":"additional","affiliation":[{"name":"Chungnam National University,Dept. of Electronics Engineering,Daejeon,South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","article-title":"Xilinx","year":"2013","journal-title":"Spartan-6 Libraries Guide for HDL Designs"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.3390\/electronics7100246"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2399455"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2005.1515755"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311188"}],"event":{"name":"2020 International SoC Design Conference (ISOCC)","location":"Yeosu, Korea (South)","start":{"date-parts":[[2020,10,21]]},"end":{"date-parts":[[2020,10,24]]}},"container-title":["2020 International SoC Design Conference (ISOCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9332802\/9332909\/09333036.pdf?arnumber=9333036","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,26]],"date-time":"2025-08-26T19:09:33Z","timestamp":1756235373000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9333036\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,10,21]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/isocc50952.2020.9333036","relation":{},"subject":[],"published":{"date-parts":[[2020,10,21]]}}}