{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,4]],"date-time":"2025-11-04T10:54:48Z","timestamp":1762253688628,"version":"3.37.3"},"reference-count":4,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,10,21]],"date-time":"2020-10-21T00:00:00Z","timestamp":1603238400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,10,21]],"date-time":"2020-10-21T00:00:00Z","timestamp":1603238400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,10,21]],"date-time":"2020-10-21T00:00:00Z","timestamp":1603238400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100003052","name":"MOTIE","doi-asserted-by":"publisher","award":["20012010"],"award-info":[{"award-number":["20012010"]}],"id":[{"id":"10.13039\/501100003052","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,10,21]]},"DOI":"10.1109\/isocc50952.2020.9333074","type":"proceedings-article","created":{"date-parts":[[2021,2,2]],"date-time":"2021-02-02T20:51:49Z","timestamp":1612299109000},"page":"57-58","source":"Crossref","is-referenced-by-count":5,"title":["Diagnosis of Scan Chain Faults Based-on Machine-Learning"],"prefix":"10.1109","author":[{"given":"Hyeonchan","family":"Lim","sequence":"first","affiliation":[]},{"given":"Tae Hyun","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Seunghwan","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Sungho","family":"Kang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2017.50"},{"key":"ref3","first-page":"1","article-title":"On Designing Two-Dimensional Scan Architecture for Test Chips","author":"huang","year":"0","journal-title":"Proc of 2017 IEEE International Symposium on VLSI Design Automation and Test (VLSI-DAT)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1995.512645"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2294712"}],"event":{"name":"2020 International SoC Design Conference (ISOCC)","start":{"date-parts":[[2020,10,21]]},"location":"Yeosu, Korea (South)","end":{"date-parts":[[2020,10,24]]}},"container-title":["2020 International SoC Design Conference (ISOCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9332802\/9332909\/09333074.pdf?arnumber=9333074","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,28]],"date-time":"2022-06-28T21:53:39Z","timestamp":1656453219000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9333074\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,10,21]]},"references-count":4,"URL":"https:\/\/doi.org\/10.1109\/isocc50952.2020.9333074","relation":{},"subject":[],"published":{"date-parts":[[2020,10,21]]}}}