{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,22]],"date-time":"2025-05-22T06:07:13Z","timestamp":1747894033636,"version":"3.37.3"},"reference-count":9,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,10,6]],"date-time":"2021-10-06T00:00:00Z","timestamp":1633478400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,10,6]],"date-time":"2021-10-06T00:00:00Z","timestamp":1633478400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,10,6]],"date-time":"2021-10-06T00:00:00Z","timestamp":1633478400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100012226","name":"Fundamental Research Funds for the Central Universities","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100012226","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,10,6]]},"DOI":"10.1109\/isocc53507.2021.9613913","type":"proceedings-article","created":{"date-parts":[[2021,11,25]],"date-time":"2021-11-25T20:31:55Z","timestamp":1637872315000},"page":"195-196","source":"Crossref","is-referenced-by-count":5,"title":["Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge Devices"],"prefix":"10.1109","author":[{"given":"Tianzhu","family":"Xiong","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yongliang","family":"Zhou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuyao","family":"Kong","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bo","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"An","family":"Guo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yufei","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chen","family":"Xue","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Haiming","family":"Hsu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xin","family":"Si","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jun","family":"Yang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2952773"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662435"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062949"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062995"},{"key":"ref8","first-page":"250","article-title":"A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips","author":"su","year":"2021","journal-title":"IEEE International Solid-State Circuits Conference"},{"key":"ref7","first-page":"252","article-title":"An 89TOPS\/W and 16.3TOPS\/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications","author":"chih","year":"2021","journal-title":"IEEE International Solid-State Circuits Conference"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3039206"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3073254"},{"key":"ref1","article-title":"Nonvolatile Circuits for Memory, Logic, and Artificial Intelligence","author":"chang","year":"2018","journal-title":"IEEE International Solid State Circuits Conference (ISSCC) tutorial"}],"event":{"name":"2021 18th International SoC Design Conference (ISOCC)","start":{"date-parts":[[2021,10,6]]},"location":"Jeju Island, Korea, Republic of","end":{"date-parts":[[2021,10,9]]}},"container-title":["2021 18th International SoC Design Conference (ISOCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9613844\/9613845\/09613913.pdf?arnumber=9613913","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T16:52:34Z","timestamp":1652201554000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9613913\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,10,6]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/isocc53507.2021.9613913","relation":{},"subject":[],"published":{"date-parts":[[2021,10,6]]}}}