{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T01:28:46Z","timestamp":1725758926643},"reference-count":4,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,10,6]],"date-time":"2021-10-06T00:00:00Z","timestamp":1633478400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,10,6]],"date-time":"2021-10-06T00:00:00Z","timestamp":1633478400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,10,6]],"date-time":"2021-10-06T00:00:00Z","timestamp":1633478400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,10,6]]},"DOI":"10.1109\/isocc53507.2021.9613957","type":"proceedings-article","created":{"date-parts":[[2021,11,25]],"date-time":"2021-11-25T20:31:55Z","timestamp":1637872315000},"page":"367-368","source":"Crossref","is-referenced-by-count":1,"title":["Power Side-Channel Analysis for Different Adders on FPGA"],"prefix":"10.1109","author":[{"given":"Yilin","family":"Zhao","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Qidi","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroki","family":"Nishikawa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiangbo","family":"Kong","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroyuki","family":"Tomiyama","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","article-title":"A toolkit for power behavior analysis of HLS-designed FPGA circuits","author":"zhang","year":"2021","journal-title":"Low-Power and High-Speed Chips"},{"key":"ref3","article-title":"A testing methodology for side-channel resistance validation","author":"goodwill","year":"2011","journal-title":"NIST Non-invasive Attack Testing Workshop"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-45234-8_68"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-48405-1_25"}],"event":{"name":"2021 18th International SoC Design Conference (ISOCC)","start":{"date-parts":[[2021,10,6]]},"location":"Jeju Island, Korea, Republic of","end":{"date-parts":[[2021,10,9]]}},"container-title":["2021 18th International SoC Design Conference (ISOCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9613844\/9613845\/09613957.pdf?arnumber=9613957","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T16:52:38Z","timestamp":1652201558000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9613957\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,10,6]]},"references-count":4,"URL":"https:\/\/doi.org\/10.1109\/isocc53507.2021.9613957","relation":{},"subject":[],"published":{"date-parts":[[2021,10,6]]}}}