{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,10]],"date-time":"2026-01-10T19:10:18Z","timestamp":1768072218512,"version":"3.49.0"},"reference-count":10,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,10,6]],"date-time":"2021-10-06T00:00:00Z","timestamp":1633478400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,10,6]],"date-time":"2021-10-06T00:00:00Z","timestamp":1633478400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,10,6]],"date-time":"2021-10-06T00:00:00Z","timestamp":1633478400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,10,6]]},"DOI":"10.1109\/isocc53507.2021.9613990","type":"proceedings-article","created":{"date-parts":[[2021,11,25]],"date-time":"2021-11-25T20:31:55Z","timestamp":1637872315000},"page":"211-214","source":"Crossref","is-referenced-by-count":7,"title":["Reducing Refresh Overhead with In-DRAM Error Correction Codes"],"prefix":"10.1109","author":[{"given":"Hanbyeol","family":"Kwon","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kwangrae","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dongsuk","family":"Jeon","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ki-Seok","family":"Chung","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.30"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2366231.2337161","article-title":"RAIDR: Retention-aware intelligent DRAM refresh","volume":"40","author":"liu","year":"2012","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218745"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2015.58"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2019.102942"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2018.2820052"},{"key":"ref2","article-title":"DDR5 SDRAM specification JESD79-5","year":"2020"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref1","article-title":"DDR4 SDRAM specification JESD79-4B","year":"2017"}],"event":{"name":"2021 18th International SoC Design Conference (ISOCC)","location":"Jeju Island, Korea, Republic of","start":{"date-parts":[[2021,10,6]]},"end":{"date-parts":[[2021,10,9]]}},"container-title":["2021 18th International SoC Design Conference (ISOCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9613844\/9613845\/09613990.pdf?arnumber=9613990","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T16:52:34Z","timestamp":1652201554000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9613990\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,10,6]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/isocc53507.2021.9613990","relation":{},"subject":[],"published":{"date-parts":[[2021,10,6]]}}}