{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,11]],"date-time":"2025-01-11T05:33:20Z","timestamp":1736573600062,"version":"3.32.0"},"reference-count":8,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,8,19]],"date-time":"2024-08-19T00:00:00Z","timestamp":1724025600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,8,19]],"date-time":"2024-08-19T00:00:00Z","timestamp":1724025600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,8,19]]},"DOI":"10.1109\/isocc62682.2024.10762463","type":"proceedings-article","created":{"date-parts":[[2024,11,29]],"date-time":"2024-11-29T18:49:10Z","timestamp":1732906150000},"page":"29-30","source":"Crossref","is-referenced-by-count":0,"title":["A Programmable DLL-based Delay Chain"],"prefix":"10.1109","author":[{"given":"Yu-Wei","family":"Huang","sequence":"first","affiliation":[{"name":"National United University,Department of Electrical Engineering,Miao-Li,Taiwan, R.O.C.,36063"}]},{"given":"Cheng-En","family":"Wu","sequence":"additional","affiliation":[{"name":"National United University,Department of Electrical Engineering,Miao-Li,Taiwan, R.O.C.,36063"}]},{"given":"Wei-Bin","family":"Yang","sequence":"additional","affiliation":[{"name":"Tamkang University,Department of Electrical and Computer Engineering,New Taipei City,Taiwan, R.O.C.,251301"}]},{"given":"Jen-Chieh","family":"Liu","sequence":"additional","affiliation":[{"name":"National United University,Department of Electrical Engineering,Miao-Li,Taiwan, R.O.C.,36063"}]}],"member":"263","reference":[{"article-title":"Jitter analysis of mixed PLL-DLL architecture in DRAM environment","volume-title":"2009 MIXDES-16th International Conference Mixed Design of Integrated Circuits & Systems","author":"Sayfullah","key":"ref1"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ASICON58565.2023.10396561"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351396"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISOCC56007.2022.10031551"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IranianCEE.2019.8786365"},{"year":"2021","key":"ref6","article-title":"3.3V ECL programmable delay chip"},{"year":"2021","key":"ref7","article-title":"2.5V\/3.3V, 3.2Gbps, precision CML dual channel programmable delay for automotive"},{"year":"2017","key":"ref8","article-title":"LVDS programmable delay line"}],"event":{"name":"2024 21st International SoC Design Conference (ISOCC)","start":{"date-parts":[[2024,8,19]]},"location":"Sapporo, Japan","end":{"date-parts":[[2024,8,22]]}},"container-title":["2024 21st International SoC Design Conference (ISOCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10761119\/10761994\/10762463.pdf?arnumber=10762463","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,10]],"date-time":"2025-01-10T19:49:55Z","timestamp":1736538595000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10762463\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,8,19]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/isocc62682.2024.10762463","relation":{},"subject":[],"published":{"date-parts":[[2024,8,19]]}}}