{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,12]],"date-time":"2026-03-12T01:04:44Z","timestamp":1773277484571,"version":"3.50.1"},"reference-count":32,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,5,22]],"date-time":"2024-05-22T00:00:00Z","timestamp":1716336000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,5,22]],"date-time":"2024-05-22T00:00:00Z","timestamp":1716336000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,5,22]]},"DOI":"10.1109\/isorc61049.2024.10551337","type":"proceedings-article","created":{"date-parts":[[2024,6,12]],"date-time":"2024-06-12T17:28:14Z","timestamp":1718213294000},"page":"1-10","source":"Crossref","is-referenced-by-count":1,"title":["Multicore DRAM Bank-& Row-Conflict Bomb for Timing Attacks in Mixed-Criticality Systems"],"prefix":"10.1109","author":[{"given":"Antonio","family":"Savino","sequence":"first","affiliation":[{"name":"Università Degli Studi di Napoli Federico II,Italy"}]},{"given":"Gautam","family":"Gala","sequence":"additional","affiliation":[{"name":"Technical University of Kaiserslautern-Landau,Germany"}]},{"given":"Marcello","family":"Cinque","sequence":"additional","affiliation":[{"name":"Università Degli Studi di Napoli Federico II,Italy"}]},{"given":"Gerhard","family":"Fohler","sequence":"additional","affiliation":[{"name":"Technical University of Kaiserslautern-Landau,Germany"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISORC52013.2021.00024"},{"key":"ref2","journal-title":"Scalable Open Architecture for Embedded Edge (SOAFEE)"},{"key":"ref3","author":"Ecker","journal-title":"What is the real-time cloud and how do we get there?"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2016.7461353"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2023.102848"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISORC52572.2022.9812757"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISORC58943.2023.00022"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3534879.3534882"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CSE.2013.106"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2019.00037"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISORC52572.2022.9812711"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2021.3108044"},{"key":"ref13","article-title":"64 and ia-32 architectures optimization reference manual","year":"2023"},{"key":"ref14","article-title":"Intel\u00ae xeon\u00ae processor scalable memory family uncore performance monitoring","year":"2020"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2016.26"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/cdc.2004.1430279"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2015.24"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2000.898056"},{"key":"ref19","article-title":"DRAMA: Exploiting DRAM addressing for Cross-CPU attacks","volume-title":"25th USENIX Security Symposium (USENIX Security 16)","author":"Pessl"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2016.7461361"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2014.6925999"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MASCOTS50786.2020.9285962"},{"key":"ref23","article-title":"Process cruise control: Throttling memory access in a soft real-time environment","volume-title":"Symposium on Operating Systems Principles","author":"Bellosa"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2012.32"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2013.6531079"},{"key":"ref26","doi-asserted-by":"crossref","DOI":"10.1145\/3316781.3317840","article-title":"Holistic multi-resource allocation for multicore real-time virtualization","volume-title":"Proceedings of the 56th Annual Design Automation Conference 2019, DAC \u201919","author":"Xu"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2017.15"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS52030.2021.00024"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/3302424.3303977"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/3302424.3303963"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/3337821.3337863"},{"key":"ref32","article-title":"Technical evaluation for the new intel memory bandwidth regulation capabilities on the real-time domain","volume-title":"master thesis","author":"Farina","year":"2020"}],"event":{"name":"2024 IEEE 27th International Symposium on Real-Time Distributed Computing (ISORC)","location":"Tunis, Tunisia","start":{"date-parts":[[2024,5,22]]},"end":{"date-parts":[[2024,5,25]]}},"container-title":["2024 IEEE 27th International Symposium on Real-Time Distributed Computing (ISORC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10551300\/10551323\/10551337.pdf?arnumber=10551337","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,6,25]],"date-time":"2024-06-25T19:10:23Z","timestamp":1719342623000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10551337\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,5,22]]},"references-count":32,"URL":"https:\/\/doi.org\/10.1109\/isorc61049.2024.10551337","relation":{},"subject":[],"published":{"date-parts":[[2024,5,22]]}}}