{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T07:49:19Z","timestamp":1725522559263},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,8]]},"DOI":"10.1109\/ispa.2014.26","type":"proceedings-article","created":{"date-parts":[[2014,10,22]],"date-time":"2014-10-22T16:07:05Z","timestamp":1413994025000},"page":"134-141","source":"Crossref","is-referenced-by-count":0,"title":["FPGA-Based Design Using the FASTER Toolchain: The Case of STM Spear Development Board"],"prefix":"10.1109","author":[{"given":"F.","family":"Spada","sequence":"first","affiliation":[]},{"given":"A.","family":"Scolari","sequence":"additional","affiliation":[]},{"given":"G.C.","family":"Durelli","sequence":"additional","affiliation":[]},{"given":"R.","family":"Cattaneo","sequence":"additional","affiliation":[]},{"given":"M.D.","family":"Santambrogio","sequence":"additional","affiliation":[]},{"given":"D.","family":"Sciuto","sequence":"additional","affiliation":[]},{"given":"D.N.","family":"Pnevmatikatos","sequence":"additional","affiliation":[]},{"given":"G.N.","family":"Gaydadjiev","sequence":"additional","affiliation":[]},{"given":"O.","family":"Pell","sequence":"additional","affiliation":[]},{"given":"A.","family":"Brokalakis","sequence":"additional","affiliation":[]},{"given":"W.","family":"Luk","sequence":"additional","affiliation":[]},{"given":"D.","family":"Stroobandt","sequence":"additional","affiliation":[]},{"given":"D.","family":"Pau","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"17","doi-asserted-by":"publisher","DOI":"10.1145\/1073204.1073211"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/PCCC.2009.5403843"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/MCSE.2010.69"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2013.6604246"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1145\/1058129.1058143"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311188"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1145\/1365490.1365500"},{"year":"0","key":"3"},{"year":"0","key":"2"},{"year":"0","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2014.32"},{"journal-title":"Efficient Circuit Specialization for Dynamic Reconfiguration of FPGAs","year":"2011","author":"bruneel","key":"7"},{"year":"0","key":"6"},{"year":"0","key":"5"},{"year":"0","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/RSP.2013.6683965"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/HPCMP-UGC.2007.79"}],"event":{"name":"2014 IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA)","start":{"date-parts":[[2014,8,26]]},"location":"Milan, Italy","end":{"date-parts":[[2014,8,28]]}},"container-title":["2014 IEEE International Symposium on Parallel and Distributed Processing with Applications"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6921428\/6924413\/06924439.pdf?arnumber=6924439","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T15:57:39Z","timestamp":1490284659000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6924439\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,8]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/ispa.2014.26","relation":{},"subject":[],"published":{"date-parts":[[2014,8]]}}}