{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T09:41:37Z","timestamp":1761990097154,"version":"build-2065373602"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,11]]},"DOI":"10.1109\/ispacs.2015.7432788","type":"proceedings-article","created":{"date-parts":[[2016,3,14]],"date-time":"2016-03-14T20:24:03Z","timestamp":1457987043000},"page":"317-322","source":"Crossref","is-referenced-by-count":3,"title":["Implementation of a high-speed flash ADC for high-performance pipeline ADCs in an 180nm CMOS process"],"prefix":"10.1109","author":[{"given":"Robert","family":"Loehr","sequence":"first","affiliation":[]},{"given":"Markus","family":"Kempf","sequence":"additional","affiliation":[]},{"given":"Frank","family":"Ohnhaeuser","sequence":"additional","affiliation":[]},{"given":"Juergen","family":"Roeber","sequence":"additional","affiliation":[]},{"given":"Robert","family":"Weigel","sequence":"additional","affiliation":[]},{"given":"Andreas","family":"Baenisch","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2004.836842"},{"key":"ref3","article-title":"Theory and Realization of High-End Analog-to-Digital Converters based on the Principle of Successive Approximation","author":"frank","year":"2008","journal-title":"University of Erlangen-Nuremberg"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1002\/9780470891179"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"599","DOI":"10.1109\/4.760369","article-title":"A 1.5-V, 10-bit, 14.3-MS\/s CMOS Pipeline Analog-to-Digital Converter","volume":"34","author":"abo andrew","year":"1999","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"ref5","article-title":"Pipeline Analog-to-Digital Converters for Wide-Band Wireless Communications","author":"lauri","year":"2002","journal-title":"Helsinki University of Technology Electronic Circuit Design Laboratory Report"},{"journal-title":"Offset Voltage Analysis of Dynamic Latched Comparator","year":"2011","author":"heungjun","key":"ref8"},{"journal-title":"A Low-offset High-speed Double-tail Dual-rail Dynamic Latched Comparator","year":"2010","author":"heungjun","key":"ref7"},{"journal-title":"Pipelined ADC Design and Enhancement Techniques","year":"2010","author":"imran","key":"ref2"},{"journal-title":"Systematic analysis and cancellation of kickback noise in a dynamic latched comparator","year":"2013","author":"ka-meng","key":"ref9"},{"journal-title":"Tutorial 1023","article-title":"Maxim Integrated: Understanding Pipelined ADCs","year":"2001","key":"ref1"}],"event":{"name":"2015 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","start":{"date-parts":[[2015,11,9]]},"location":"Nusa Dua Bali, Indonesia","end":{"date-parts":[[2015,11,12]]}},"container-title":["2015 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7428504\/7432721\/07432788.pdf?arnumber=7432788","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,24]],"date-time":"2017-06-24T08:18:34Z","timestamp":1498292314000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7432788\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,11]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/ispacs.2015.7432788","relation":{},"subject":[],"published":{"date-parts":[[2015,11]]}}}