{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,30]],"date-time":"2025-09-30T10:36:28Z","timestamp":1759228588205,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,11]]},"DOI":"10.1109\/ispacs.2018.8923180","type":"proceedings-article","created":{"date-parts":[[2019,12,6]],"date-time":"2019-12-06T01:46:00Z","timestamp":1575596760000},"page":"43-47","source":"Crossref","is-referenced-by-count":3,"title":["Low Power Source Biased Semi-Adiabatic Logic Circuit for IoT Devices"],"prefix":"10.1109","author":[{"given":"Cancio","family":"Monteiro","sequence":"first","affiliation":[]},{"given":"Apolinario","family":"Maria","sequence":"additional","affiliation":[]},{"given":"Yasuhiro","family":"Takahashi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"1437","article-title":"Carry propagation free adder\/subtractor VLSI using adiabatic dynamic CMOS logic circuit technology","volume":"e86 a","author":"takahashi","year":"2003","journal-title":"IEICE Trans Fundamentals"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1093\/ietele\/e90-c.10.2002"},{"key":"ref12","first-page":"17","article-title":"Two-phase clocked CMOS adiabatic logic","volume":"3","author":"takahashi","year":"2009","journal-title":"Far East J Electronics and Communications"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"1","DOI":"10.5573\/JSTS.2010.10.1.001","article-title":"Two phase clocked adiabatic static CMOS logic and its logic family","volume":"10","author":"nayan","year":"2010","journal-title":"J Semiconductor Technology and Science"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2013.04.003"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2011.12.013"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/92.335009"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.1994.573218"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1587\/elex.12.20150695"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1049\/el:19961272"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/4.499727"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2017.2653058"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2627369.2631644"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/92.863629"}],"event":{"name":"2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","start":{"date-parts":[[2018,11,27]]},"location":"Ishigaki, Okinawa, Japan","end":{"date-parts":[[2018,11,30]]}},"container-title":["2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8910142\/8923116\/08923180.pdf?arnumber=8923180","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,1,30]],"date-time":"2020-01-30T23:33:03Z","timestamp":1580427183000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8923180\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,11]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/ispacs.2018.8923180","relation":{},"subject":[],"published":{"date-parts":[[2018,11]]}}}