{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T23:20:32Z","timestamp":1725578432577},"reference-count":13,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,11,16]],"date-time":"2021-11-16T00:00:00Z","timestamp":1637020800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,11,16]],"date-time":"2021-11-16T00:00:00Z","timestamp":1637020800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,11,16]],"date-time":"2021-11-16T00:00:00Z","timestamp":1637020800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,11,16]]},"DOI":"10.1109\/ispacs51563.2021.9651069","type":"proceedings-article","created":{"date-parts":[[2021,12,28]],"date-time":"2021-12-28T21:29:56Z","timestamp":1640726996000},"page":"1-2","source":"Crossref","is-referenced-by-count":0,"title":["A Scan-Based Lower-Power Testing Architecture for Modern Circuits"],"prefix":"10.1109","author":[{"given":"Jiann-Chyi","family":"Rau","sequence":"first","affiliation":[]},{"given":"Jia-Xiang","family":"Wang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2016.7805828"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2017.7918357"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DEVIC.2017.8074022"},{"journal-title":"Digital Systems Testing and Testable Design","year":"1990","author":"abramovici","key":"ref13"},{"journal-title":"VLSI Test Principles and Architectures Design for Testability (Systems on Silicon)","year":"2006","author":"laung-terng","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/EWDTS.2016.7807675"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2606248"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2608984"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/43.998630"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2016.7805826"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2000.843824"},{"key":"ref1","first-page":"1","article-title":"California scan architecture for high quality and low power testing","author":"cho","year":"2007","journal-title":"Test Conference 2007 ITC 2007 IEEE International"},{"key":"ref9","first-page":"1","article-title":"Staggered ATPG with capture-per-cycle observation test points","author":"yingdi","year":"2018","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"}],"event":{"name":"2021 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","start":{"date-parts":[[2021,11,16]]},"location":"Hualien City, Taiwan","end":{"date-parts":[[2021,11,19]]}},"container-title":["2021 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9650918\/9650920\/09651069.pdf?arnumber=9651069","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T17:00:02Z","timestamp":1652202002000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9651069\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,11,16]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/ispacs51563.2021.9651069","relation":{},"subject":[],"published":{"date-parts":[[2021,11,16]]}}}