{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T13:34:36Z","timestamp":1742391276512},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2005]]},"DOI":"10.1109\/ispass.2005.1430558","type":"proceedings-article","created":{"date-parts":[[2008,7,18]],"date-time":"2008-07-18T15:07:52Z","timestamp":1216393672000},"page":"42-53","source":"Crossref","is-referenced-by-count":4,"title":["A High Performance, Energy Efficient GALS ProcessorMicroarchitecture with Reduced Implementation Complexity"],"prefix":"10.1109","author":[{"family":"YongKang Zhu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.H.","family":"Albonesi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Buyuktosunoglu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"13","doi-asserted-by":"publisher","DOI":"10.1145\/1024393.1024423"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2004.1299297"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2002.995696"},{"key":"3","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"2","article-title":"Early stage definition of LPX: A low power issue-execute processor","author":"bose","year":"2002","journal-title":"Proceedings of the 2nd International Workshop on Power-aware Computer Systems in Conjunction with the 8th International Symposium on High Performance Computer Architecture"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1240208"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2002.1176263"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003573"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003572"},{"key":"5","doi-asserted-by":"crossref","DOI":"10.1109\/ASYNC.2003.1199168","article-title":"Efficient self-timed interfaces for crossing clock domains","author":"chakraborty","year":"2003","journal-title":"Proc 9th Int Symp Asynchronous Circuits and Systems"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/268806.268810"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1997.604689"},{"key":"8","doi-asserted-by":"crossref","DOI":"10.1145\/871656.859621","article-title":"Profile-based dynamic voltage and frequency scaling for a multiple clock domain processor","author":"magklis","year":"2003","journal-title":"Proc International Symposium on Computer Architecture"}],"event":{"name":"IEEE International Symposium on Performance Analysis of Systems and Software, 2005. ISPASS 2005.","start":{"date-parts":[[2005,3,20]]},"location":"Austin, TX, USA","end":{"date-parts":[[2005,3,22]]}},"container-title":["IEEE International Symposium on Performance Analysis of Systems and Software, 2005. ISPASS 2005."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9783\/30850\/01430558.pdf?arnumber=1430558","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T10:01:41Z","timestamp":1497780101000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1430558\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/ispass.2005.1430558","relation":{},"subject":[],"published":{"date-parts":[[2005]]}}}