{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T08:06:24Z","timestamp":1730275584651,"version":"3.28.0"},"reference-count":30,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/ispass.2006.1620800","type":"proceedings-article","created":{"date-parts":[[2006,4,28]],"date-time":"2006-04-28T07:05:46Z","timestamp":1146207946000},"page":"154-165","source":"Crossref","is-referenced-by-count":1,"title":["Automatic testcase synthesis and performance model validation for highperformance PowerPC processors"],"prefix":"10.1109","author":[{"given":"R.H.","family":"Bell","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.R.","family":"Bhatia","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L.K.","family":"John","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Stuecheli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Griswell","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.","family":"Tu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L.","family":"Capps","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Blanchard","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.","family":"Thai","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/40.768496"},{"journal-title":"Memory Bandwidth and Machine Balance in Current High Performance Computers","year":"1995","author":"mccalpin","key":"17"},{"key":"18","first-page":"279","article-title":"Lmbench: Portable tools for performance analysis","author":"mcvoy","year":"1996","journal-title":"USENIX Technical Conference"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1147\/rd.446.0851"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1147\/rd.461.0053"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.1"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.33"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/43.736182"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1147\/sj.403.0781"},{"year":"0","key":"21"},{"key":"20","first-page":"71","article-title":"HLS: combining statistical and symbolic simulation to guide microprocessor designs","author":"oskin","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2002.995700"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605403"},{"key":"24","article-title":"Performance analysis and validation of the intel Pentium4 processor on 90nm technology","volume":"8","author":"singhal","year":"2004","journal-title":"Intel Tech J"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1147\/rd.494.0505"},{"year":"0","key":"26"},{"key":"27","first-page":"344","article-title":"Architectural performance verification: PowerPC processors","author":"surya","year":"1999","journal-title":"Proceedings of the IEEE International Conference on Computer Design"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1147\/rd.461.0005"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1147\/rd.494.0541"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/1088149.1088164"},{"journal-title":"Experiments in Automatic Benchmark Synthesis","year":"2004","author":"bell jr","key":"2"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2004.1310787"},{"key":"1","article-title":"Deconstructing and improving statistical simulation in HLS","author":"bell jr","year":"2004","journal-title":"Workshop on Duplicating Deconstructing and Debunking (WDDD) in Conjunction with ISCA"},{"key":"30","article-title":"SMARTS: Accelerating microarchitecture simulation via rigorous statistical sampling","author":"wunderlich","year":"2002","journal-title":"IEEE International Symposium on Computer Architecture"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/2.675632"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1147\/rd.446.0885"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/2.675637"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2005.1526007"},{"key":"9","article-title":"Modeling superscalar processors via statistical simulation","author":"carl","year":"1998","journal-title":"Workshop on Performance Analysis and its Impact on Design"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1994.315635"}],"event":{"name":"2006 IEEE International Symposium on Performance Analysis of Systems and Software","location":"Austin, TX, USA"},"container-title":["2006 IEEE International Symposium on Performance Analysis of Systems and Software"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10781\/33948\/01620800.pdf?arnumber=1620800","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,14]],"date-time":"2017-03-14T18:33:17Z","timestamp":1489516397000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1620800\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":30,"URL":"https:\/\/doi.org\/10.1109\/ispass.2006.1620800","relation":{},"subject":[]}}