{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T23:45:49Z","timestamp":1729640749166,"version":"3.28.0"},"reference-count":31,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,4]]},"DOI":"10.1109\/ispass.2009.4919651","type":"proceedings-article","created":{"date-parts":[[2009,5,11]],"date-time":"2009-05-11T18:22:49Z","timestamp":1242066169000},"page":"195-206","source":"Crossref","is-referenced-by-count":1,"title":["Analysis of the TRIPS prototype block predictor"],"prefix":"10.1109","author":[{"given":"Nitya","family":"Ranganathan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Doug","family":"Burger","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stephen W.","family":"Keckler","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859667"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1995.476809"},{"article-title":"combining hyperblocks and exit prediction to increase front-end bandwidth and performance","year":"2002","author":"ranganathan","key":"18"},{"article-title":"combining branch predictors","year":"1993","author":"mcfarling","key":"15"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2001.991104"},{"key":"13","first-page":"65","article-title":"head and tail duplication for convergent hyperblock formation","author":"maher","year":"2006","journal-title":"International Symposium on Microarchitecture"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1992.696999"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605420"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2005.6"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.13"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.19"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1145\/237090.237169"},{"key":"23","article-title":"a case for (partially) tagged geometric history length predictor","author":"seznec","year":"2006","journal-title":"Journal of Instruction-Level Parallelism"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2001.953283"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2003.1183524"},{"key":"26","article-title":"speculative updates of local and global branch history: a quantitative analysis","volume":"2","author":"skadron","year":"2000","journal-title":"Journal of Instruction-Level Parallelism"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2006.10"},{"key":"28","doi-asserted-by":"crossref","first-page":"170","DOI":"10.1145\/291069.291042","article-title":"variable length path branch prediction","author":"stark","year":"1998","journal-title":"Architectural Support for Programming Languages and Operating Systems"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2003.1207010"},{"key":"3","doi-asserted-by":"crossref","first-page":"3","DOI":"10.1145\/232974.232975","article-title":"using hybrid predictors to improve branch prediction accuracy in the presence of context switches","author":"evers","year":"1996","journal-title":"International Symposium on Computer Architecture"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1995.476834"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/40.755465"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1145\/237090.237171"},{"journal-title":"An Infrastructure for Research in Instruction-Level Parallelism","year":"0","key":"30"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645793"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1997.569673"},{"key":"5","first-page":"191","article-title":"increasing the instruction fetch rate via block-structured instruction set architectures","author":"hao","year":"1996","journal-title":"International Symposium on Microarchitecture"},{"key":"31","doi-asserted-by":"publisher","DOI":"10.1145\/165939.165956"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694762"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903263"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.40"}],"event":{"name":"Software (ISPASS)","start":{"date-parts":[[2009,4,26]]},"location":"Boston, MA, USA","end":{"date-parts":[[2009,4,28]]}},"container-title":["2009 IEEE International Symposium on Performance Analysis of Systems and Software"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4907867\/4919623\/04919651.pdf?arnumber=4919651","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,3,13]],"date-time":"2024-03-13T07:29:43Z","timestamp":1710314983000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4919651\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,4]]},"references-count":31,"URL":"https:\/\/doi.org\/10.1109\/ispass.2009.4919651","relation":{},"subject":[],"published":{"date-parts":[[2009,4]]}}}