{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,7]],"date-time":"2025-08-07T08:58:52Z","timestamp":1754557132491},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,4]]},"DOI":"10.1109\/ispass.2011.5762716","type":"proceedings-article","created":{"date-parts":[[2011,5,9]],"date-time":"2011-05-09T20:41:43Z","timestamp":1304973703000},"page":"66-75","source":"Crossref","is-referenced-by-count":19,"title":["Memory access pattern-aware DRAM performance model for multi-core systems"],"prefix":"10.1109","author":[{"given":"Hyojin","family":"Choi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jongbok","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wonyong","family":"Sung","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.1039"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MASCOT.2004.1348302"},{"journal-title":"DDR3 SDRAM Standard","year":"2008","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/342001.339668"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.82"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/195470.195547"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"24","DOI":"10.1109\/ISCA.1995.524546","article-title":"The SPLASH-2 programs: characterization and methodological considerations","author":"woo","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"key":"ref17","doi-asserted-by":"crossref","DOI":"10.1145\/360128.360134","article-title":"A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality","author":"zhang","year":"2000","journal-title":"Proc ACM\/IEEE Int Symp Microarchitecture"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1140389.1140396"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/SUPERC.1990.130001"},{"journal-title":"XDR datasheet","year":"2002","key":"ref4"},{"journal-title":"Memory Systems Cache DRAM Disk","year":"2007","author":"jacob","key":"ref3"},{"key":"ref6","article-title":"The design space of data-parallel memory systems","author":"ahn","year":"2006","journal-title":"Proc ACM\/IEEE Conf Supercomputing"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346190"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/71.139201"},{"key":"ref7","article-title":"A hybrid analytical DRAM performance model","author":"yuan","year":"2009","journal-title":"Proc Workshop on Modeling Benchmarking and Simulation"},{"journal-title":"Computer Architecture A Quantitative Approach","year":"2006","author":"hennessy","key":"ref2"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2010.107"}],"event":{"name":"Software (ISPASS)","start":{"date-parts":[[2011,4,10]]},"location":"Austin, TX, USA","end":{"date-parts":[[2011,4,12]]}},"container-title":["(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5755445\/5762705\/05762716.pdf?arnumber=5762716","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,6,6]],"date-time":"2023-06-06T17:54:41Z","timestamp":1686074081000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5762716\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,4]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/ispass.2011.5762716","relation":{},"subject":[],"published":{"date-parts":[[2011,4]]}}}