{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,3]],"date-time":"2025-10-03T18:14:49Z","timestamp":1759515289258,"version":"3.28.0"},"reference-count":33,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,4]]},"DOI":"10.1109\/ispass.2012.6189219","type":"proceedings-article","created":{"date-parts":[[2012,5,1]],"date-time":"2012-05-01T21:14:48Z","timestamp":1335906888000},"page":"125-134","source":"Crossref","is-referenced-by-count":11,"title":["Data sharing in multi-threaded applications and its impact on chip design"],"prefix":"10.1109","author":[{"given":"Anil","family":"Krishna","sequence":"first","affiliation":[]},{"given":"Ahmad","family":"Samih","sequence":"additional","affiliation":[]},{"given":"Yan","family":"Solihin","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","first-page":"25","article-title":"Impact of data sharing on CMP design: A study based on analytical modeling","author":"krishna","year":"2011","journal-title":"2nd Intl Workshop on New Frontiers in High Performance and Hardware Aware Computing HipHaC11"},{"journal-title":"Intel 22nm 3-D Tri-Gate Transistor Technology","year":"2011","key":"17"},{"journal-title":"Assembly and Packaging","year":"2007","key":"18"},{"key":"33","article-title":"Performance, area, and bandwidth implications for large scale CMP cache design","author":"zhao","year":"2007","journal-title":"CMP-MSI"},{"key":"15","first-page":"199","article-title":"Exploring the design space of future CMPs","author":"huh","year":"2001","journal-title":"Proceedings International Conference on Parallel Architectures and Compilation Techniques PACT-02"},{"year":"2009","key":"16"},{"year":"2010","key":"13"},{"key":"14","doi-asserted-by":"crossref","DOI":"10.1145\/1105734.1105739","article-title":"Exploring the cache design space for large scale cmps","volume":"33","author":"hsu","year":"2005","journal-title":"SIGArch Computer Architecture News"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.77"},{"key":"12","first-page":"1","article-title":"On the nature of cache miss behavior: Is it ?2?","volume":"10","author":"hartstein","year":"2008","journal-title":"Journal of Instruction-Level Parallelism"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/ICGRID.2006.311019"},{"key":"20","article-title":"The cost of uncore in throughput-oriented many-core processors","author":"loh","year":"2008","journal-title":"Proc of Workshop on Architectures and Languages for Troughput Applications (ALTA)"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1145\/1284621.1284622"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250670"},{"journal-title":"MIPS 1004K Processor","year":"2010","key":"25"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2009.27"},{"key":"27","first-page":"2","article-title":"New microarchitecture challenges in the coming generations of CMOS process technologies (keynote address)","author":"pollack","year":"1999","journal-title":"Proc 31st Annu ACM\/IEEE Int Symp on Microarchitecture"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555801"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1145\/1095408.1095421"},{"year":"2011","key":"3"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/1465482.1465560"},{"journal-title":"Power Scaling The Ultimate Obstacle to 1K-Core Chips","year":"2010","author":"hardavellas","key":"10"},{"journal-title":"Using compression to improve chip multiprocessor performance","year":"2006","author":"alameldeen","key":"1"},{"key":"30","article-title":"Core count vs cache size for manycore architectures in the cloud","author":"wentzlaff","year":"2010","journal-title":"Tech Rep MITCSAIL-TR-2010-008"},{"key":"7","doi-asserted-by":"crossref","first-page":"93","DOI":"10.1145\/1629911.1629940","article-title":"design perspectives on 22nm cmos and beyond","author":"borkar","year":"2009","journal-title":"2009 46th ACM\/IEEE Design Automation Conference dac"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"32","doi-asserted-by":"publisher","DOI":"10.1145\/1693453.1693482"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1177\/109434209100500306"},{"key":"31","article-title":"Scaling single-program performance on large-scale chip multiprocessors","author":"wu","year":"2009","journal-title":"Tech Rep UMIACS-TR-2009-16 University of Maryland"},{"year":"2010","key":"4"},{"key":"9","first-page":"365","article-title":"Dark silicon and the end of multicore scaling","author":"esmaeilzadeh","year":"2011","journal-title":"2011 38th Annual International Symposium on Computer Architecture (ISCA) ISCA"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1145\/1941487.1941507"}],"event":{"name":"2012 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS)","start":{"date-parts":[[2012,4,1]]},"location":"New Brunswick, NJ, USA","end":{"date-parts":[[2012,4,3]]}},"container-title":["2012 IEEE International Symposium on Performance Analysis of Systems &amp; Software"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6182687\/6189192\/06189219.pdf?arnumber=6189219","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T18:11:17Z","timestamp":1497982277000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6189219\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,4]]},"references-count":33,"URL":"https:\/\/doi.org\/10.1109\/ispass.2012.6189219","relation":{},"subject":[],"published":{"date-parts":[[2012,4]]}}}