{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T01:15:10Z","timestamp":1725412510560},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,4]]},"DOI":"10.1109\/ispass.2012.6189223","type":"proceedings-article","created":{"date-parts":[[2012,5,1]],"date-time":"2012-05-01T17:14:48Z","timestamp":1335892488000},"page":"168-177","source":"Crossref","is-referenced-by-count":5,"title":["A single-pass cache simulation methodology for two-level unified caches"],"prefix":"10.1109","author":[{"given":"Wei","family":"Zang","sequence":"first","affiliation":[]},{"given":"Ann","family":"Gordon-Ross","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1145\/1366110.1366129"},{"key":"22","article-title":"Performance evaluation of exclusive cache hierarchies","author":"zheng","year":"2004","journal-title":"IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)"},{"journal-title":"Efficient Simulation of Multiple Cache Configurations Using Binomial Trees","year":"1991","author":"sugumar","key":"17"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1145\/58564.59296"},{"journal-title":"MIPS32 4KTM Processor Core Family Software User's Manual","year":"2001","key":"15"},{"key":"16","article-title":"Low power design techniques for micropocessors","author":"segars","year":"2001","journal-title":"IEEE International Solid-State Circuits Conference"},{"key":"13","doi-asserted-by":"crossref","first-page":"241","DOI":"10.1145\/344166.344610","article-title":"a low power unified cache architecture providing power and performance flexibility","author":"malik","year":"2000","journal-title":"ISLPED 00 the 2000 International Symposium on Low Power Electronics and Design (Cat No 00TH8514) LPE-00"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1147\/sj.92.0078"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2006.1594783"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645830"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1145\/993396.993405"},{"year":"0","key":"3"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2011.5722226"},{"year":"0","key":"2"},{"year":"0","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/12.40842"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/1027084.1027086"},{"year":"0","key":"6"},{"year":"0","key":"5"},{"key":"4","article-title":"Evaluating future microprocessors: The simplescalar toolset","author":"burger","year":"2000","journal-title":"Technical Report CS-TR-1308"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2002459"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364686"}],"event":{"name":"2012 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS)","start":{"date-parts":[[2012,4,1]]},"location":"New Brunswick, NJ, USA","end":{"date-parts":[[2012,4,3]]}},"container-title":["2012 IEEE International Symposium on Performance Analysis of Systems & Software"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6182687\/6189192\/06189223.pdf?arnumber=6189223","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,28]],"date-time":"2019-06-28T00:13:58Z","timestamp":1561680838000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6189223\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,4]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/ispass.2012.6189223","relation":{},"subject":[],"published":{"date-parts":[[2012,4]]}}}