{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,2]],"date-time":"2026-07-02T23:51:15Z","timestamp":1783036275570,"version":"3.54.6"},"reference-count":62,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,3]]},"DOI":"10.1109\/ispass.2014.6844483","type":"proceedings-article","created":{"date-parts":[[2014,7,15]],"date-time":"2014-07-15T17:41:31Z","timestamp":1405446091000},"page":"190-200","source":"Crossref","is-referenced-by-count":181,"title":["NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads"],"prefix":"10.1109","author":[{"given":"Seth H","family":"Pugsley","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jeffrey","family":"Jestes","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Huihui","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Rajeev","family":"Balasubramonian","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Vijayalakshmi","family":"Srinivasan","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Alper","family":"Buyuktosunoglu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Al","family":"Davis","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Feifei","family":"Li","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"35","year":"0","journal-title":"International Technology Roadmap for Semiconductors 2009 edition"},{"key":"36","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242474"},{"key":"33","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454152"},{"key":"34","article-title":"A 48-core ia-32 message-passing processor with dvfs in 45nm cmos","author":"howard","year":"2010","journal-title":"Proceedings of ISSCC"},{"key":"39","author":"keckler","year":"2011","journal-title":"Life after Dennard and How i Learned to Love the Picojoule"},{"key":"37","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416642"},{"key":"38","article-title":"FlexRAM: Toward an advanced intelligent memory system","author":"kang","year":"1999","journal-title":"Proceedings of ICCD"},{"key":"43","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485926"},{"key":"42","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.37"},{"key":"41","article-title":"On-die interconnects for next generation cmps","author":"kundu","year":"2006","journal-title":"Work- Shop on On- And Off-Chip Interconnection Networks for Multicore Sys- Tems (OCIN)"},{"key":"40","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176969"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2010.50"},{"key":"23","year":"2009","journal-title":"News Release Elpida Completes Development of Cu-TSV (Through Silicon Via) Multi-Layer 8-Gigabit DRAM"},{"key":"24","year":"2011","journal-title":"News Release Elpida PTI and UMC Partner on 3D IC Integration Development for Advanced Technologies Including 28nm"},{"key":"25","doi-asserted-by":"crossref","first-page":"45","DOI":"10.1145\/2094114.2094126","article-title":"SAP hana database: Data management for modern business applications","volume":"40","author":"fa?rber","year":"2011","journal-title":"SIGMOD Record"},{"key":"26","first-page":"28","article-title":"The sap hana database - An architecture overview","volume":"35","author":"fa?rber","year":"2012","journal-title":"IEEE Data Eng Bull"},{"key":"27","author":"farrell","year":"2012","journal-title":"HMC Overview A Revolutionary Approach to System Memory"},{"key":"28","article-title":"Centip3De: A 3930 dmips\/w configurable near- threshold 3d stacked system with 64 arm cortex-m3 cores","author":"fick","year":"2012","journal-title":"Proceedings of ISSCC"},{"key":"29","article-title":"VIRAM-1: A media-oriented vector processor with embedded dram","author":"gebis","year":"2004","journal-title":"Proceedings of DAC"},{"key":"3","year":"0","journal-title":"Hybrid Memory Cube Micron Technologies"},{"key":"2","year":"0","journal-title":"Hotspot 5 0"},{"key":"1","year":"0","journal-title":"Cortex-A5 Processor"},{"key":"7","year":"0","journal-title":"PUMA Benchmarks and Dataset Downloads"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155660"},{"key":"6","year":"0","journal-title":"Micron System Power Calculator"},{"key":"5","year":"0","journal-title":"Memcached A Distributed Memory Object Caching System"},{"key":"32","article-title":"Mapping irregular applications to diva, a pim-based data- intensive architecture","author":"hall","year":"1999","journal-title":"Proceedings of SC"},{"key":"4","year":"0","journal-title":"Intel Xeon Processor E5-4650 Specifications"},{"key":"31","article-title":"AC-dimm: Associative computing with stt-mram","author":"guo","year":"2013","journal-title":"Proceedings of ISCA"},{"key":"9","year":"2011","journal-title":"Open-Silicon and Micron Align to Deliver Next-Generation Memory Technology"},{"key":"8","year":"0","journal-title":"Wind River Simics Full-System Simulator"},{"key":"59","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798259"},{"key":"58","year":"0","journal-title":"SAS In-Memory Analytics"},{"key":"57","year":"0","journal-title":"Memory Computing SAP HANA"},{"key":"56","article-title":"DRAM scaling and bandwidth challenges","author":"sandhu","year":"2012","journal-title":"NSF Work- Shop on Emerging Technologies for Interconnects (WETI)"},{"key":"19","article-title":"Breaking the speed and scalability barriers for graph exploration on distributed-memory machines","author":"checconi","year":"2012","journal-title":"Proceedings of SC"},{"key":"55","year":"2005","journal-title":"Samsung Electronics Develops World's First Eight-Die Multi-Chip Package for Multimedia Cell Phones"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1145\/2212908.2212915"},{"key":"18","author":"chatterjee","year":"2012","journal-title":"USIMM The Utah Simulated Memory Module"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1145\/1054943.1054946"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508270"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1815967"},{"key":"14","year":"0","journal-title":"Berkeley DB High-performance Embedded Database for Key\/value Data"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1145\/1629575.1629577"},{"key":"12","author":"arlitt","year":"1998","journal-title":"1998 World Cup Web Site Access Logs"},{"key":"21","article-title":"MapReduce for the cell b.E. Architecture","volume":"53","author":"dekruijf","year":"2009","journal-title":"IBM Journal of Research and Development"},{"key":"20","article-title":"MapReduce: Simplified data processing on large clusters","author":"dean","year":"2004","journal-title":"Proceedings of OSDI"},{"key":"62","article-title":"Spark: Cluster computing with working sets","author":"zaharia","year":"2010","journal-title":"The Proceedings of Hot-cloud"},{"key":"60","year":"2011","journal-title":"3D Stacked DRAM\/Bi-STAR Overview"},{"key":"61","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416628"},{"key":"49","doi-asserted-by":"publisher","DOI":"10.1145\/1713254.1713276"},{"key":"48","article-title":"Active pages: A model of computation for intelligent memory","author":"oskin","year":"1998","journal-title":"Proceedings of ISCA"},{"key":"45","article-title":"A thermally-aware performance analysis of vertically integrated (3-d) processor-memory hierarchy","author":"loi","year":"2006","journal-title":"Proceedings of DAC-43"},{"key":"44","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.15"},{"key":"47","article-title":"The characterization of data intensive memory workloads on distributed pim systems","author":"murphy","year":"2000","journal-title":"Proceed- Ings of Workshop on Intelligent Memory Systems"},{"key":"46","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798261"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/1140402.1140405"},{"key":"51","article-title":"Hybrid memory cube (hmc)","author":"pawlowski","year":"2011","journal-title":"HOTCHIPS"},{"key":"52","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2011.18"},{"key":"53","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346181"},{"key":"54","year":"2010","journal-title":"Samsung to Release 3D Memory Modules with 50% Greater Density"},{"key":"50","doi-asserted-by":"publisher","DOI":"10.1109\/40.592312"}],"event":{"name":"2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)","location":"CA, USA","start":{"date-parts":[[2014,3,23]]},"end":{"date-parts":[[2014,3,25]]}},"container-title":["2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6832911\/6844447\/06844483.pdf?arnumber=6844483","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T12:46:07Z","timestamp":1498135567000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6844483\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,3]]},"references-count":62,"URL":"https:\/\/doi.org\/10.1109\/ispass.2014.6844483","relation":{},"subject":[],"published":{"date-parts":[[2014,3]]}}}