{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T22:53:20Z","timestamp":1725404000604},"reference-count":34,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,4]]},"DOI":"10.1109\/ispass.2017.7975265","type":"proceedings-article","created":{"date-parts":[[2017,7,13]],"date-time":"2017-07-13T20:47:13Z","timestamp":1499978833000},"page":"3-12","source":"Crossref","is-referenced-by-count":2,"title":["Sharing the instruction cache among lean cores on an asymmetric CMP for HPC applications"],"prefix":"10.1109","author":[{"given":"Ugljesa","family":"Milic","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alejandro","family":"Rico","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paul","family":"Carpenter","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alex","family":"Ramirez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2013.6654614"},{"key":"ref32","article-title":"Cacti 3.0: An integrated cache timing, power, and area model","author":"shivakumar","year":"2001","journal-title":"Compaq Computer Corporation Tech Rep"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.814327"},{"key":"ref30","article-title":"Cortex-A15 &#x201C;Eagle&#x201D; flies the coop","author":"turley","year":"2010","journal-title":"Microprocessor Report"},{"key":"ref34","article-title":"Comparing multiported cache schemes","author":"niar","year":"2003","journal-title":"PDPTA"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1996.566447"},{"key":"ref13","article-title":"Increasing the instruction fetch rate via multiple branch prediction and a branch address cache","author":"yeh","year":"2014","journal-title":"ACM International Conference on Supercomputing 25th Anniversary Volume"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2008.224"},{"journal-title":"Tech Rep","article-title":"NVIDIA Tegra 4 Family CPU Architecture","year":"2013","key":"ref15"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2503210.2503281"},{"key":"ref17","article-title":"Nvidia's First CPU Is a Winner","author":"gwennap","year":"2014","journal-title":"Microprocessor Report"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2006.6"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508274"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2011.5762718"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2008.209"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1080695.1070004"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1465482.1465560"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2016.7581273"},{"key":"ref29","article-title":"Papi: A portable interface to hardware performance counters","author":"mucci","year":"1999","journal-title":"Proceedings of the Department of Defense HPCMP Users Group Conference"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2005.379"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.41"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/232973.232993"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.108"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.23"},{"journal-title":"Intel Xeon Phi Coprocessor High-performance Programming","year":"2013","author":"jeffers","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1816011"},{"journal-title":"Cash Revisiting hardware sharing in single-chip parallel processor","year":"2002","author":"dolbeau","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.12"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/1152923.1024297"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/773365.773369"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1999.765954"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISSOC.2011.6089691"}],"event":{"name":"2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)","start":{"date-parts":[[2017,4,24]]},"location":"Santa Rosa, CA, USA","end":{"date-parts":[[2017,4,25]]}},"container-title":["2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7965804\/7975258\/07975265.pdf?arnumber=7975265","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,8,16]],"date-time":"2017-08-16T16:19:39Z","timestamp":1502900379000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7975265\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,4]]},"references-count":34,"URL":"https:\/\/doi.org\/10.1109\/ispass.2017.7975265","relation":{},"subject":[],"published":{"date-parts":[[2017,4]]}}}