{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,27]],"date-time":"2026-05-27T07:03:09Z","timestamp":1779865389562,"version":"3.53.1"},"reference-count":36,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,4,26]],"date-time":"2026-04-26T00:00:00Z","timestamp":1777161600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,4,26]],"date-time":"2026-04-26T00:00:00Z","timestamp":1777161600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,4,26]]},"DOI":"10.1109\/ispass69572.2026.00043","type":"proceedings-article","created":{"date-parts":[[2026,5,26]],"date-time":"2026-05-26T19:39:19Z","timestamp":1779824359000},"page":"369-379","source":"Crossref","is-referenced-by-count":0,"title":["Understanding BTB Tag Sizing"],"prefix":"10.1109","author":[{"given":"Roman K.","family":"Brunner","sequence":"first","affiliation":[{"name":"Norwegian University of Science and Technology,Trondheim,Norway"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Rakesh","family":"Kumar","sequence":"additional","affiliation":[{"name":"Norwegian University of Science and Technology,Trondheim,Norway"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","article-title":"IBM z16 (3931)technical guide. Section 3.4.3, page 84"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/isca45697.2020.00014"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2021.3109945"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA56546.2023.10070938"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1167473.1167488"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522308"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/micro61859.2024.00102"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508281"},{"key":"ref9","article-title":"ChampSim Simulator"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.14778\/2732240.2732246"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1995.476826"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC59245.2023.00027"},{"key":"ref13","doi-asserted-by":"crossref","DOI":"10.1145\/2155620.2155638","article-title":"Proactive Instruction Fetch","volume-title":"International Symposium on Microarchitecture","author":"Ferdman"},{"key":"ref14","article-title":"The Championship Simulator: Architectural Simulation for Education and Competition","author":"Gober","year":"2022"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3620665.3640394"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00015"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/3528416.3530224"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44520-X_134"},{"key":"ref19","article-title":"1st Instruction Prefetching Championship Traces"},{"key":"ref20","doi-asserted-by":"crossref","DOI":"10.1145\/2540708.2540732","article-title":"SHIFT: Shared History Instruction Fetch for Lean-core Server Processors","volume-title":"International Symposium on Microarchitecture","author":"Kaynak"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830785"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480124"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3484492"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173178"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.53"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/isca59077.2024.00012"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00050"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA59077.2024.00089"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.2972222"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/3314221.3314637"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1999.809439"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/HCS49909.2020.9220508"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/232973.232985"},{"key":"ref34","article-title":"A 64-kbytes ittage indirect branch predictor","author":"Seznec","year":"2011","journal-title":"J. Instruction-Level Parallelism"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/3470496.3527430"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480046"}],"event":{"name":"2026 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)","location":"Seoul, Korea, Republic of","start":{"date-parts":[[2026,4,26]]},"end":{"date-parts":[[2026,4,28]]}},"container-title":["2026 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11527204\/11527232\/11527249.pdf?arnumber=11527249","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,5,27]],"date-time":"2026-05-27T06:13:47Z","timestamp":1779862427000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11527249\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,4,26]]},"references-count":36,"URL":"https:\/\/doi.org\/10.1109\/ispass69572.2026.00043","relation":{},"subject":[],"published":{"date-parts":[[2026,4,26]]}}}