{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T19:51:47Z","timestamp":1725565907212},"reference-count":11,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/isqed.2004.1283676","type":"proceedings-article","created":{"date-parts":[[2004,5,6]],"date-time":"2004-05-06T20:18:03Z","timestamp":1083874683000},"page":"217-222","source":"Crossref","is-referenced-by-count":1,"title":["Functional vector generation for combinational circuits based on data path coverage metric and mixed integer linear programming"],"prefix":"10.1109","author":[{"given":"J.","family":"Sosa","sequence":"first","affiliation":[]},{"given":"J.A.","family":"Montiel-Nelson","sequence":"additional","affiliation":[]},{"given":"H.","family":"Navarro","sequence":"additional","affiliation":[]},{"given":"J.C.","family":"Garcia","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/54.936247"},{"journal-title":"System-On-A-Chip Verification Methodology and Techniques","year":"2001","author":"rashihkar","key":"2"},{"journal-title":"GNU Linear Programming Kit Reference Manual","year":"2003","author":"makhorin","key":"10"},{"key":"1","article-title":"Logic synthesis and optimization benchmarks user guide version 3.0","author":"yang","year":"1991","journal-title":"Rep Microelectronics Center of North Carolina"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2001.915055"},{"key":"6","doi-asserted-by":"crossref","first-page":"528","DOI":"10.1145\/277044.277187","article-title":"Functional vector generation for HDL models using linear programming and 3-satisfiability","author":"fallah","year":"1998","journal-title":"Proceedings 1998 Design and Automation Conference 35th DAC (Cat No 98CH36175) DAC"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1994.292317"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1996.545595"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-2219-2"},{"key":"8","first-page":"526","article-title":"Algorithms for solving boolean satisfiability in combinational circuits","author":"guerra e silva","year":"1999","journal-title":"Proceeding of Design Automation and Test in Europe"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1987.1270347"}],"event":{"name":"5th International Symposium on Quality Electronic Design","acronym":"ISQED-04","location":"San Jose, CA, USA"},"container-title":["SCS 2003. International Symposium on Signals, Circuits and Systems. Proceedings (Cat. No.03EX720)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9029\/28654\/01283676.pdf?arnumber=1283676","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T06:52:36Z","timestamp":1497595956000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1283676\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/isqed.2004.1283676","relation":{},"subject":[]}}