{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T06:52:06Z","timestamp":1725432726256},"reference-count":12,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/isqed.2004.1283719","type":"proceedings-article","created":{"date-parts":[[2004,5,6]],"date-time":"2004-05-06T20:18:03Z","timestamp":1083874683000},"page":"478-482","source":"Crossref","is-referenced-by-count":6,"title":["IPQ: IP qualification for efficient system design"],"prefix":"10.1109","author":[{"given":"H.-J.","family":"Brand","sequence":"first","affiliation":[]},{"given":"S.","family":"Rulke","sequence":"additional","affiliation":[]},{"given":"M.","family":"Radetzki","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","article-title":"IP configuration management with abstract parameterizations","author":"lang","year":"2002","journal-title":"IP-Based SOC Design"},{"doi-asserted-by":"publisher","key":"2","DOI":"10.1007\/3-540-45006-8_39"},{"key":"10","article-title":"IP qualification","author":"radetzki","year":"2002","journal-title":"Intellectual Property Design and Integration for System-on-chip Tutorial Notes of the Design Automation Conference (DAC)"},{"year":"0","key":"1"},{"key":"7","article-title":"Model checking in an industrial environment","author":"fordran","year":"2003","journal-title":"GI\/ITG\/GMM-Workshop Methoden Beschreibungssprachen Modellierung Verifikation von Schaltungen Systemen"},{"key":"6","article-title":"Shrinking the parameter space of IP by utilizing parameter domains","author":"jerinic","year":"2002","journal-title":"IP-Based SOC Design"},{"key":"5","article-title":"A next generation interconnect concept to design high performance SoC's","author":"demuth","year":"2002","journal-title":"IP-Based SOC Design"},{"doi-asserted-by":"publisher","key":"4","DOI":"10.1007\/978-0-387-35599-3_27"},{"doi-asserted-by":"publisher","key":"9","DOI":"10.1109\/ISQED.2002.996698"},{"doi-asserted-by":"publisher","key":"8","DOI":"10.1109\/DSD.2002.1115393"},{"key":"11","article-title":"DAVe - A design guideline analyzer for verilog","author":"rogin","year":"2002","journal-title":"Proc Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS)"},{"key":"12","article-title":"IP-qualification, reuse, IP-packaging","author":"vo?rg","year":"2001","journal-title":"Forum on Design Languages"}],"event":{"acronym":"ISQED-04","name":"5th International Symposium on Quality Electronic Design","location":"San Jose, CA, USA"},"container-title":["SCS 2003. International Symposium on Signals, Circuits and Systems. Proceedings (Cat. No.03EX720)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9029\/28654\/01283719.pdf?arnumber=1283719","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,14]],"date-time":"2017-03-14T02:37:48Z","timestamp":1489459068000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1283719\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/isqed.2004.1283719","relation":{},"subject":[]}}